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MAX1265 Datasheet(Fiches technique) 4 Page - Maxim Integrated Products

Numéro de pièce MAX1265
Description  265ksps, 3V, 6-/2-Channel, 12-Bit ADCs with 2.5V Reference and Parallel Interface
Télécharger  19 Pages
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Fabricant  MAXIM [Maxim Integrated Products]
Site Internet  http://www.maxim-ic.com
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 4 page
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265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
tTR
20
70
ns
CLOAD = 20pF, Figure 1
RD Rise to Output Disable
WR to CLK Fall Setup Time
tCWS
40
ns
ns
CLK Pulse Width High
ns
CLK Period
tCH
40
RD Fall to Output Data Valid
tDO
20
70
ns
RD Fall to INT High Delay
tINT1
100
ns
CS Fall to Output Data Valid
tDO2
110
ns
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
CLOAD = 20pF, Figure 1
tCP
208
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR Setup Time
tCSWS
60
ns
CLK or WR to CS Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width
tWR
60
ns
tTC
20
100
ns
(Note 8)
CLOAD = 20pF, Figure 1
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
CS Rise to Output Disable
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
6k
3k
DOUT
DOUT
VDD
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
CLOAD
20pF
CLOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times




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