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M32171F4VFP Datasheet(Fiches technique) 29 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32171F4VFP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER    
Télécharger  37 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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 29 page
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Mitsubishi Microcomputers
29
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32171 Group
3-channel High-speed Serial I/Os
The microcomputer contains three channels of serial I/Os
consisting of two channels that can be set for CSIO mode
(clock-synchronized serial I/O) or UART mode (asynchro-
nous serial I/O) and one other channel that can only be set
for UART mode.
The SIO has the function to generate a DMA transfer re-
quest when data reception is completed or the transmit reg-
ister becomes empty, and is capable of high-speed serial
communication without causing any additional CPU load.
Table 14 Outline of Serial I/O
Item
Content
Number of channels
CSIO/UART: 2 channels (SIO0,SIO1)
UART only : 1 channels (SIO2)
Clock
During CSIO mode : Internal clock / external clock, selectable (Note1)
During UART mode : Internal clock only
Transfer mode
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
BRG count sourcef
(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2)
Data format
CSIO mode :
Data length = Fixed to 8 bits
Order of transfer = Fixed to LSB first
UARTmode :
Start bit = 1 bit
Character length = 7, 8, or 9 bits
Parity bit = Added or not added (When added, selectable between odd and even parity)
Stop bit = 1 or 2 bits
Order of transfer = Fixed to LSB first
Baud rate
CSIO mode :
152 bits per second to 2 Mbits per second (when operating with f(BCLK) = 20 MHz)
UARTmode :
19 bits per second to 156 Kbits per second (when operating with f(BCLK) = 20 MHz)
Error detection
CSIO mode :
Overrun error only
UARTmode :
Overrun, parity, and framing errors
(The error-sum bit indicates which error has occurred)
Fixed cycle clock
When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin.
output function
Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16.
Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations.




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