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M32171F4VFP Datasheet(Fiches technique) 20 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32171F4VFP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER    
Télécharger  37 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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Mitsubishi Microcomputers
20
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32171 Group
Item
Content
Number of channels
10 channels
Transfer request
• Software trigger
• Request from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O
(reception completed, transmit buffer empty)
• Cascaded connection between DMA channels possible (Note)
Maximum number of times transferred256 times
Transferable address space
• 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF)
• Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO,
and between internal RAMs are supported
Transfer data size
16 bits or 8 bits
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer performed),
dual-address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination of transfer:
• Address fixed
• Address increment
• 32-channel ring buffer
Channel priority
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 >
channel 5 > channel 6 > channel 7 > channel 8 > channel 9
(Fixed priority)
Maximum transfer rate
13.3 Mbytes per second (when internal peripheral clock = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows
Transfer area
64 Kbytes from H’0080 0000 to H’0080 FFFF (Transfer is possible in the entire internal
RAM/SFR area)
Note: The following DMA channels can be cascaded.
DMA transfer on channel 1 started at end of one DMA transfer on channel 0
DMA transfer on channel 2 started at end of one DMA transfer on channel 1
DMA transfer on channel 0 started at end of one DMA transfer on channel 2
DMA transfer on channel 4 started at end of one DMA transfer on channel 3
DMA transfer on channel 6 started at end of one DMA transfer on channel 5
DMA transfer on channel 7 started at end of one DMA transfer on channel 6
DMA transfer on channel 5 started at end of one DMA transfer on channel 7
DMA transfer on channel 9 started at end of one DMA transfer on channel 8
DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register)
Built-in 10-Channel DMAC
The microcomputer contains 10 channels of DMAC, allowing
for data transfer between internal peripheral I/Os, between
internal RAM and internal peripheral I/O, and between inter-
nal RAMs.
DMA transfer requests can be issued from the user-cre
ated software, as well as can be triggered by a signal gener-
ated by the internal peripheral I/O (A-D converter, MJT, or
serial I/O).
Table 11 Outline of the DMAC
The microcomputer also supports cascaded connection be-
tween DMA channels (starting DMA transfer on a channel at
end of transfer on another channel). This makes advanced
transfer processing possible without causing any additional
CPU load.




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