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M32171F4VFP Datasheet(Fiches technique) 33 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32171F4VFP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER    
Télécharger  37 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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Mitsubishi Microcomputers
33
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32171 Group
CPU Instruction Set
The M32R employs a RISC architecture, supporting a total
of 83 discrete instructions.
(1) Load/store instructions
Perform data transfer between memory and registers.
LD
Load
LDB
Load byte
LDUB
Load unsigned byte
LDH
Load halfword
LDUH
Load unsigned halfword
LOCK
Load locked
ST
Store
STB
Store byte
STH
Store halfword
UNLOCK
Store unlocked
(2) Transfer instructions
Perform register to register transfer or register to immediate
transfer
.
LD24
Load 24-bit immediate
LDI
Load immediate
MV
Move register
MVFC
Move from control register
MVTC
Move to control register
SETH
Set high-order 16-bit
(3) Branch instructions
Used to change the program flow.
BC
Branch on C-bit
BEQ
Branch on equal
BEQZ
Branch on equal zero
BGEZ
Branch on greater than or equal zero
BGTZ
Branch on greater than zero
BL
Branch and link
BLEZ
Branch on less than or equal zero
BLTZ
Branch on less than zero
BNC
Branch on not C-bit
BNE
Branch on not equal
BNEZ
Branch on not equal zero
BRA
Branch
JL
Jump and link
JMP
Jump
NOP
No operation
(4) Arithmetic/logic instructions
Perform comparison, arithmetic/logic operation, multiplica-
tion/division, or shift between registers.
• Comparison
CMP
Compare
CMPI
Compare immediate
CMPU
Compare unsigned
CMPUI
Compare unsigned immediate
• Logical operation
AND
AND
AND3
AND 3-operand
NOT
Logical NOT
OR
OR
OR3
OR 3-operand
XOR
Exclusive OR
XOR3
Exclusive OR 3-operand
• Arithmetic operation
ADD
Add
ADD3
Add 3-operand
ADDI
Add immediate
ADDV
Add (with overflow checking)
ADDV3
Add 3-operand
ADDX
Add with carry
NEG
Negate
SUB
Subtract
SUBV
Subtract (with overflow checking)
SUBX
Subtract with borrow
• Multiplication/division
DIV
Divide
DIVU
Divide unsigned
MUL
Multiply
REM
Remainder
REMU
Remainder unsigned
• Shift
SLL
Shift left logical
SLL3
Shift left logical 3-operand
SLLI
Shift left logical immediate
SRA
Shift right arithmetic
SRA3
Shift right arithmetic 3-operand
SRAI
Shift right arithmetic immediate
SRL
Shift right logical
SRL3
Shift right logical 3-operand
SRLI
Shift right logical immediate
(5) Instructions for the DSP function
Perform 32 bit
× 16 bit or 16 bit × 16 bit multiplication or sum-
of-products calculation. These instructions also perform
rounding of the accumulator data or transfer between accu-
mulator and general-purpose register.
MACHI
Multiply-accumulate high-order
halfwords
MACLO
Multiply-accumulate low-order
halfwords
MACWHI
Multiply-accumulate word and
high-order halfword
MACWLO
Multiply-accumulate word and
low-order halfword
MULHI
Multiply high-order halfwords
MULLO
Multiply low-order halfwords
MULWHI
Multiply word and high-order
halfword
MULWLO
Multiply word and low-order
halfword
MVFACHI
Move from accumulator high-order word
MVFACLO
Move from accumulator low-order word
MVFACMI
Move from accumulator middle-order
word
MVTACHI
Move to accumulator high-order word
MVTACLO
Move to accumulator low-order word
RAC
Round accumulator
RACH
Round accumulator halfword
(6) EIT related instructions
Start trap or return from EIT processing.
RTE
Return from EIT
TRAP
Trap




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