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BUJ103AD Fiches technique(PDF) 7 Page - NXP Semiconductors |
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BUJ103AD Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 13 page BUJ103AD All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 8 November 2011 7 of 13 NXP Semiconductors BUJ103AD Silicon diffused power transistor 7. Package information Epoxy meets requirements of UL94 V-0 at 1⁄8 inch. VCEclamp 1000 V; VCC = 150 V; VBB = 5 V; LB =1 H; LC =200 H. Tj Tj(max). Fig 13. Test circuit for reverse bias safe operating area Fig 14. Reverse bias safe operating area Tmb 25 C; Mounted with heatsink compound and 30 5 Newton force on the center of the envelope. (1) Ptot maximum and Ptot peak maximum lines. (2) Second breakdown limits. (3) I = Region of permissible DC operation. II = Extension for repetitive pulse operation. III = Extension during turn-on in single transistor converters provided that RBE 100 and tp 0.6 s. Fig 15. Forward bias safe operating area 001aab999 DUT LC LB IBon VBB VCC VCL(CE) probe point VCEclamp (V) 0 1000 800 400 600 200 001aac000 4 6 2 8 10 IC (A) 0 001aac001 10−1 10−2 10 1 102 IC (A) 10−3 VCEclamp (V) 1 103 102 10 (1) 100 μs 200 μs I(3) tp = 20 μs duty cycle = 0.01 50 μs 500 μs DC II(3) III(3) (2) ICM(max) IC(max) |
Numéro de pièce similaire - BUJ103AD_15 |
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Description similaire - BUJ103AD_15 |
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