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M32000D4BFP-80 Datasheet(Fiches technique) 26 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32000D4BFP-80
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER   
Télécharger  44 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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 26 page
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
26
M32000D4BFP-80
(master)
ROM
ASIC
PP0
M/S
M/S
HREQ
INT
M32000D4BFP-80
(slave)
HACK
HREQ
HACK
bus
arbiter
INT
Master/slave mode
_
The M32000D4BFP-80 has an M/S (master/slave) pin for multipro-
cessor configuration use.
_
• master mode (M/S = "H")
_
This is normal operation mode. Set the M/S pin to an "H" level. It is
used when the M32000D4BFP-80 is used as the main CPU in a
system.
_
• slave mode (M/S = "L")
This operation mode is for when the M32000D4BFP-80 is used as a
_
coprocessor. Set the M/S pin to an "L" level. When set to slave mode,
the M32000D4BFP-80 does not start operation even after a reset,
until an interrupt request or the SBI is input. Processing is carried out
by communicating with the master M32000D4BFP-80, using the two
programmable I/O ports and the external interrupt signal.
D24
D25
D26
D27
D28
D29
D30
D31
LM
lock control register (MLCR) < address: H'FFFF FFF7>
Fig. 26 Lock control register
______
0: HREQ
exclusive
lock mode
___
1: CS exclusive
lock mode
R = 0 ... "0" when reading
R =
... read enabled
W =
... write enabled
W =
: write disabled
<at reset: H'00>
D
bit name
function
R
W
24 - 30
Not
0
!
assigned.
31
LM
(lock mode)
• Coprocessor only configuration example
The slave M32000D4BFP-80 accesses only the internal DRAM and
_
_____
never the external bus. M/S and HREQ are fixed at the "L" level. The
slave M32000D4BFP-80 executes the instructions that the master
M32000D4BFP-80 downloads to the internal DRAM. The data trans-
fer request (processing complete) from the slave M32000D4BFP-80
is notified to the master M32000D4BFP-80 by inputting the interrupt
request via the programmable I/O port. The data transaction is car-
ried out when the master M32000D4BFP-80 accesses the internal
DRAM in the slave M32000D4BFP-80.
• Common bus coprocessor configuration example
In this configuration, the slave M32000D4BFP-80 can also access
the external bus. Communications between the master and slave
CPUs is carried out using the programmable I/O ports and the inter-
rupt request input.
<coprocessor only configuration>
<common bus coprocessor configuration>
Fig. 27 Master/slave system configuration example
M32000D4BFP-80
(master)
ROM
ASIC
INT
PP0
M/S
M/S
HREQ
INT
M32000D4BFP-80
(slave)
no access to
external bus
!




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