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M32000D4BFP-80 Datasheet(Fiches technique) 19 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32000D4BFP-80
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER   
Télécharger  44 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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 19 page
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
19
Bus interface unit (BIU)
The M32000D4BFP-80 has the following signals related to the exter-
nal bus.
• Address (A8 to A30)
The M32000D4BFP-80 has a 24-bit address bus (A8 to A31) corre-
sponding to a 16 MB address space. Of these, A31 (the LSB) is not
output externally. In write cycles, the validity of the two bytes output
___
___
on the 16-bit data bus is indicated by BCH and/or BCL. In read
cycles, the 16-bit data bus is always read, however, only data in the
valid byte position in the M32000D4BFP-80 is transferred. The ad-
dress pins are bidirectional. If the M32000D4BFP-80 is in the hold
state and the internal DRAM is accessed from an external bus mas-
ter, the address signal is input from the system bus side.
• Space identifier (SID)
The space identifier is used to specify user space and I/O space.
user space: SID = "L"
I/O space: SID = "H"
hold: SID = high-impedance
idle: SID = undefined
___
___
• Byte control (BCH, BCL)
Byte control signals indicate the byte position of valid data trans-
___
ferred of the external bus cycle. BCH corresponds to the MSB side
________
(D0 to D7), and BCL corresponds to the LSB side (D8 to D15). Dur-
___
___
ing the read bus cycle, both BCH and BCL are an "L" level. During
___
___
the write bus cycle, BCH and/or BCL go to an "L" level depending on
the bytes to be written. If the M32000D4BFP-80 is in the hold state
and the internal DRAM is accessed from an external bus master, the
byte control signal is input from the system bus side.
• Data bus (D0 to D15)
The M32000D4BFP-80 has a 16-bit data bus to access external de-
vices. If the M32000D4BFP-80 is in the hold state and the internal
DRAM is accessed from an external bus master, the data bus is
used as a data I/O bus from the system bus side.
__
• Bus start (BS)
When the M32000D4BFP-80 drives the bus cycle to the system bus,
__
an "L" level is output to BS at the start of the bus cycle. Also, for a
__
__
burst transfer, the BS signal is output for each transfer cycle. The BS
signal is not output when accessing internal resources such as the
internal DRAM or internal I/O registers.
• Bus status (ST)
The ST signal identifies whether the bus cycle the M32000D4BFP-
80 is driving is an instruction fetch cycle or an operand access cycle.
instruction fetch access: ST = "L"
operand access: ST = "H"
hold: ST = high-impedance
idle: ST = undefined
__
• Read/write (R/W)
__
The M32000D4BFP-80 outputs a R/W signal to identify whether the
external bus cycle is a read or write operation. When accessing the
__
internal DRAM from an external bus master, a R/W signal is input
from the system bus side.
__
read bus cycle: R/W = "H"
__
write bus cycle: R/W = "L"
______
• Burst (BURST)
The M32000D4BFP-80 drives two consecutive bus cycles to access
32-bit data located on the 32-bit boundary. In instruction fetching, it
drives a maximum of 8 (fixed to 8 cycles in instruction cache mode)
consecutive read cycles to access data located on the 128-bit bound-
ary. While driving these consecutive bus cycles, the M32000D4BFP-
______
80 outputs "L" level to BURST. When accessing 32-bit data, the ad-
dress of the MSB-side 16 bits are output before the address of the
LSB side 16 bits. When accessing 128-bit data, the addresses are
output for every access cycle from the arbitrary 16-bit aligned ad-
dresses to wraparound within the 128-bit boundary.
__
• Data complete (DC)
When starting an external bus cycle, the M32000D4BFP-80 auto-
__
matically inserts wait cycles until the DC signal is input from external.
__
Wait control using the DC signal is effective also for bus cycles dur-
ing burst transfer. When the M32000D4BFP-80 is in the hold state
__
__
and if the CS signal is input, the M32000D4BFP-80 outputs the DC
signal to notify the external bus master that internal DRAM access is
complete.
_____
_____
• Hold control (HREQ, HACK)
The hold state is the state when the external bus access stops and
all pins go to a high-impedance state. However, the internal DRAM
can be accessed while the external bus is in the hold state. To put
_____
the M32000D4BFP-80 into the hold state, input an "L" level to HREQ.
When the hold request is accepted and the M32000D4BFP-80 en-
_____
ters the hold state, an "L" level is output from HACK.




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