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M32000D3FP Datasheet(Fiches technique) 25 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32000D3FP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER  
Télécharger  45 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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 25 page
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
25
("L" output)
("L" output)
("L" output)
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
V
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
write
write
write
write
SID
Note: "Hi-z" means high impedance, and
indicates sampling timing.
The value of the R/W signal that controls the data direction of the bus interface
cannot be changed during CS="L". Hold this value while CS="L".
Also, where marked above with V, 3 to 7 CLKIN clock periods are necessary for writing
operation to internal DRAM crossing an 128-bit boundary. Hold the input value of the
address or other control signals during these wait cycle periods (DC = "H"). Consecutive
writing operations within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle period, CS cannot be returned to "H" level (the access
cannot be aborted). CS can only be returned to a "H" level after DC is driven to "L".
When the M32000D3FP is in the hold state and an "L" level is input
__
to CS, the M32000D3FP interprets it as a bus access request to the
__
internal DRAM. In this case, when the R/W signal is at an "L" level,
the memory controller drives a write cycle to the internal DRAM. Byte
____
___
data control is specified by the BCH and BCL signals. Only data in
____
___
the byte positions for which an "L" level is input to BCH or BCL are
__
written. When writing is complete, an "L" level DC signal is output.
The M32000D3FP stores the requested data in the 128-bit data buffer
of the BIU, before writing to the internal DRAM. This reduces the
number of accesses to the internal DRAM when a request to writing
to consecutive addresses is made, and improves bus cycle through-
put. Consecutive write cycles within an 128-bit boundary are com-
pleted in 1 CLKIN clock period. 3 to 7 CLKIN clock periods are nec-
essary for a write access crossing an 128-bit boundary when writing
__
to the internal DRAM. After DC outputs an "L" level (access com-
__
plete), return CS to the "H" level between the CLKIN falling edge
corresponding to the last write cycle and the following CLKIN falling
______
edge. Return HREQ to the "H" level to return the M32000D3FP to
the normal operation mode from the hold state either at the same
__
time as or after CS is returned to the "H" level.
When the external bus master makes an access, the value of the
__
R/W signal that controls the data direction of the bus interface can-
__
not be changed during CS="L". Therefore, read cycles and write cycles
__
cannot be mixed while CS = "L". When starting a write cycle follow-
ing after a read cycle and starting a read cycle following a write cycle,
__
keep the CS signal at an "H" level for at least 1 CLKIN.
Fig. 24 Write bus cycle to internal DRAM
Fig. 25 Read/write bus cycle
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
("L" output)
read
CS = "H"
write
("L" output)
SID
("L" input)
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
V
"Hi-z"
"Hi-z"
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Also, where marked above with V, keep CS signal to "H" at least 1 CLKIN when
starting a write bus cycle after a read bus cycle or a read bus cycle after a write
bus cycle.
"Hi-z"




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