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M32000D3FP Datasheet(Fiches technique) 20 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32000D3FP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER  
Télécharger  45 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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 20 page
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
20
Read and write operations of the M32000D3FP are carried out using
___
_______
_______
_____
the address bus, data bus, and the R/W, BCH, BCL and DC signals.
___
_______
When reading, the R/W signal goes to an "H" level, and the BCH and
_______
BCL signals go to an "L" level. The CPU reads the data in the valid
___
byte positions. When writing, an "L" level is output from R/W, and
_______
_______
BCH and BCL are output according to the valid byte positions, so as
to specify the byte positions for writing into an external device.
Keep DC signal at the "H" level during idle cycles.
idle
read
"H"
"H"
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
idle
read
idle
write
idle
write
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
"H"
"Hi-z"
"Hi-z"
"Hi-z"
"Hi-z"
Note: "Hi-z" means high-impedance, and
indicates sampling timing.
Fig. 16 Read/write timing (two no-wait accesses)
__
• Internal DRAM access control (CS)
__
The internal DRAM can be accessed when CS is driven to an "L"
____
level after the M32000D3FP enters the hold state (HACK = "L").
To access the internal DRAM from external, the following signals
from the system bus side should be controlled.
• A8 to A30
Input internal DRAM addresses to be read or written.
___
___
• BCH, BCL
Specify the byte position of data to be written into the internal
___
___
DRAM. BCH corresponds to the MSB side (D0 to D7), and BCL
corresponds to the LSB side (D8 to D15).
__
• R/W
___
Specify read or write operation. When reading, R/W = "H". When
__
writing, R/W = "L".
• D0 to D15
16-bit data I/O bus.
• SID
When accessing the internal DRAM from an external bus mas-
ter, an "L" level is input to SID to specify user space.
_____
• DC
This signal notifies to an external bus master that the internal
DRAM access is complete. When access is complete, an "L"
_____
level is output to DC.
Table 1 Pin condition in hold state
pin name
pin condition or operation
A8 - A30, SID,
high-impedance
____
____
BCH, BCL
__
___
______
ST, R/W, BS, BURST
D0 - D15
output when internal DRAM is read
__
by an external bus master (CS = "L",
__
R/W = "H"), otherwise high-impedance
__
DC
output when internal DRAM is
accessed by an external bus master
__
(CS = "L"), otherwise high-impedance
_____
HACK
output "L"
other pins
normal operation




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