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M32000D3FP Datasheet(Fiches technique) 9 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M32000D3FP
Description  SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER  
Télécharger  45 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D3FP
9
FUNCTIONAL DESCRIPTION
CPU
The M32R CPU has 16 general-purpose registers, 5 control regis-
ters, an accumulator and a program counter. The accumulator is of
64-bit width. The registers and program counter are of 32-bit width.
General-purpose registers
The 16 general-purpose registers (R0 - R15) are of 32-bit width and
are used to retain data and base addresses. R14 is used as the link
register and R15 as the stack pointer (SPI or SPU). The link register
is used to store the return address when executing a subroutine call
instruction. The interrupt stack pointer (SPI) and the user stack pointer
(SPU) are alternatively represented by R15 depending on the value
of the stack mode bit (SM) in the processor status word register (PSW).
Control registers
There are 5 control registers which are the processor status word
register (PSW), the condition bit register (CBR), the interrupt stack
pointer (SPI), the user stack pointer (SPU) and the backup PC (BPC).
The MVTC and MVFC instructions are used for writing and reading
these control registers.
R0
R1
R2
R3
R4
R5
R6
R7
31
0
R8
R9
R10
R11
R12
R13
R14 (link register)
R15 (stack pointer)
31
0
(see note)
Note: The interrupt stack pointer (SPI) and the user stack pointer (SPU) are
alternatively represented by R15 depending on the value of the stack
mode bit (SM) in the PSW.
Fig. 1 General-purpose registers
processor status word register
condition bit register
interrupt stack pointer
user stack pointer
backup PC
31
0
CR0
CR1
CR2
CR3
CR6
(see notes)
CRn
Notes 1: CRn (n = 0 - 3, 6) denotes the control register number.
2: The MVTC and MVFC instructions are used for writing
and reading these control registers.
PSW
CBR
SPI
SPU
BPC
Fig. 2 Control registers




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