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M30623M4A Datasheet(Fiches technique) 94 Page - Mitsubishi Electric Semiconductor

Numéro de pièce M30623M4A
Description  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Télécharger  237 Pages
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Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
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Serial I/O
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
94
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART transmit/receive control register 2
Symbol
Address
When reset
UCON
03B016
X00000002
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Always set to "0"
Reserved bit
Invalid
Invalid
Invalid
CLK/CLKS select
bit 1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
UART2 special mode register
Symbol
Address
When reset
U2SMR
037716
0016
b7
b6
b5
b4 b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
ABSCS
ACSE
SSS
IIC mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCLL sync output
enable bit
Bus collision detect
sampling
clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
1 : IIC mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Ordinary
1 : Falling edge of RxD2
0 : Disabled
1 : Enabled
Transmit start condition
select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Note 1: Nothing but "0" may be written.
Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS
= “0”, the U2SMR3 register cannot be read or written to.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4: UART2 clock synchronous serial I/O mode cannot be used in M16C/62A (80-pin version) group.
(Note 1)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
SDDS
0
SDA digital delay select
bit (Note 2, Note 3)
Must always be “0”
0 : Analog delay output
is selected
1 : Digital delay output
is selected
(must always be “0” when
not using I C mode)
2
Figure 1.14.8. Serial I/O-related registers (5)




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