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LF3370QC12 Fiches technique(PDF) 8 Page - LOGIC Devices Incorporated |
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LF3370QC12 Fiches technique(HTML) 8 Page - LOGIC Devices Incorporated |
8 / 24 page LF3370 High-Definition Video Format Converter 8 03/13/2001–LDS.3370-F Video Imaging Products DEVICES INCORPORATED halfband filters to the data flowing through the LF3370. A latched HIGH to LOW transition on SYNC control signal is neededtoinitializethedevicetomarkthe beginning of valid data. In addition, if 4:2:2 interleaved video data is desired for input or output, a HIGH to LOW transition on SYNC must be registeredbyasimultaneousrisingedgeof CLK and CLK/2. CLK/2 is an internal clock that must be synchronized to CLK by use of RESET only if the core is running at half the rate of CLK (see RESET discussio n and Figures 4 & 5). Furthermore,SYNCisusedtoidentifyone interleaveddatasetfromanother. For example,inthecaseofinterleaved Chroma, Cb and Cr samples must be properly demultiplexed and synchro- nized for processing. TodifferentiateaCbsamplefromCr,there needs to be a HIGH to LOW transition on SYNC on the first Cb sample (see Figure 4 & 5); SYNC can also be toggled on every Cbsampleforre-synchronization. In the case that Cb is the first valid data word, SYNC may be used only once in device initialization and kept low until re- synchronizationisdesired. Therefore, when there is a HIGH to LOW transition on SYNC, the following is assumed: Cb will occur on the first LOW on SYNC that is latched, Cb will occur every two clock cyclesifinterleavedChromaispresented to the input port B12-0, Cb will occur every 4 clock cycles if single channel 4:2:2 interleavedvideoispresentedtotheinput port A12-0. SYNC control signal is also used to synchronize the interpolation/decimation outputdatafromtheHalf-BandFilterto the Output Multiplexer. This synchroniza- tion is done automatically. RESET RESET should be used when initializing the device for proper operation. It is used to synchronize the LF3370 core clock to the master clock. In the case that single channel 4:2:2 interleaved video data is desired either on the input or output, thus using only one input or one output port (not including Key data), the internal clock rate will be half (CLK/2) of the master clock rate (CLK). In this case, RESET is needed to synchronize the rising edge of CLK/2 to a known rising edge of CLK (see Figure 4). For example, after configuringtheLF3370andbefore streaming valid data through the part, a RESET event should be used to align the clockedges(seeFigure4&5). Furthermore,RESETwillclearHF0 and HF1. A LOW state detected on RESET on a rising edge of clock will clear flags HF0 and HF1 on the following rising edge of clock. Please note HBLANK should be FIGURE 10. HBLANK AND COUNTER CLK HBLANK 1 2 3 Data values at output of Input LUT section 5 6 7 8 10 13 911 HF0 HF1 412 14 20-bit COUNTER 17 16 18 * 0 12 3 4 5 6 78 9 10 0 1 4 5 23 15 DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11 DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11 DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11 DN+3 DN+4 DN+5 DN+6 DN+7 DN+8 DN+9 DN+10 DN+11 A'12-0* C'12-0* D'12-0* B'12-0* DN HBLANK Word A DN DN DN HBLANK Word B HBLANK Word C HBLANK Word D HBLANK Word A HBLANK Word B HBLANK Word C HBLANK Word D In this example, HF0 Count Value is set to 3 and HF1 Count Value is set to 5 FIGURE 9. OUTPUT BIAS FIGURE 8. INPUT BIAS R0 R3 13 2 13 INBIAS1-0 13 13 From Input Demux R0 R3 13 2 OUTBIAS1-0 13 13 From Core |
Numéro de pièce similaire - LF3370QC12 |
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Description similaire - LF3370QC12 |
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