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Moteur de recherche de fiches techniques de composants électroniques |
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LF3320QC12 Fiches technique(PDF) 8 Page - LOGIC Devices Incorporated |
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LF3320QC12 Fiches technique(HTML) 8 Page - LOGIC Devices Incorporated |
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8 / 24 page  DEVICES INCORPORATED LF3320 Horizontal Digital Image Filter 2-8 08/16/2000–LDS.3320-N Video Imaging Products 28 clock cycles from the first data input, DIN15-0; device latency for the first result is 11 clock cycles (11+17 = 28). The result will appear at the corresponding filter output, DOUT15-0. Subsequently, for both dual and single filter mode configurations, the sum of products will continue to appear every clock cycle thereafter until the matrix dimension has been realized. The total pipeline latency for a complete [8x8][8x1] matrix-vector operation is 26 clock cycles and the total pipeline latency for a complete [16x16][16x1] matrix-vector operation is 43 clock cycles. Therefore, to process two square matrices simultaneoulsy, of size N=8, a total of 73 clock cycles are all that is required. Similarly, to process a single square matrix, of size N=16, a total of 283 clock cycles are required. Once again, the timing diagrams (see Figure 8 and 9) will assume that the ConfigurationRegisters,thecoefficient sets, and the data values have been loaded. The corresponding timing diagram loading sequence for the coefficient banks and Configuration/Control registers are included in the LF3320 data sheets (Figure 11 and Figure 12 respectively). Further reference to timing diagram loading sequence for the RSL registers are also included in the device data sheet (Figure 15, Figure 14, and Figure 13). The Filter A and Filter B LF InterfaceTM are used to load data into the Filter A and Filter B Configura- tion Registers and coefficient banks. The Matrix Multiplication Mode is valid in the Double Wide Data/Coefficient Mode. However, there are some special considerations when this mode is desired. The LF3320 must be configured for single filter mode only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (see Table 7). Double Wide Data/Coefficient Mode FIGURE 9. SINGLE FILTER, MATRIX MULTIPLY TIMING SEQUENCE DIN11-0 I/D REGISTERS FILTER A FILTER B DOUT15-0 I/D REGISTERS R.S.L. CIRCUIT 12 16 SCALE RIN11-0 12 FIGURE 10. DOUBLE WIDE DATA/COEFFICIENT MODE CLK DIN11-0 CAB7-0 CENA / CENB 1 2 DATA SET 0 RIN11-0 CF00 CAA7-0 3 CF01 CF02 CF0A SHENA / SHENB * 11 Clocks - First Output of First Data/Coefficient Set ** 16 Clocks - End of First Data/Coefficient Set *** 26 Clocks - Final Output of First Data/Coefficient Set 1 Data Set with 16 Coefficient Sets CF0B CF0C CF0D DATA SET 0 DOUT15-0 OUT0 OUT1 11* 12 13 14 CF0E 16** OUT15 26*** OUT2 OUT3 OUT4 OUT5 CF0F OUT6 CF10 15 17 TXFRA/ TXFRB |
Numéro de pièce similaire - LF3320QC12 |
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Description similaire - LF3320QC12 |
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