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MX25R512F Fiches technique(PDF) 51 Page - Macronix International

No de pièce MX25R512F
Description  Wide Vcc Range, 512K-BIT
Download  85 Pages
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Fabricant  MCNIX [Macronix International]
Site Internet  http://www.macronix.com
Logo MCNIX - Macronix International

MX25R512F Fiches technique(HTML) 51 Page - Macronix International

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ADVANCED INFORMATION
REV. 0.00, FEB. 17, 2015
MX25R512F
P/N: PM2189
9-24. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The 4PP operation frequency supports as fast as f4PP. The other function descriptions are as same as standard
page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 30. 4 x I/O Page Program (4PP) Sequence
A20
A21 A17
A16 A12 A8 A4 A0
A13 A9 A5 A1
D4 D0
D5 D1
2
1
3456789
6 ADD cycles
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data
Byte 4
0
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
SCLK
CS#
SIO0
SIO1
SIO3
SIO2
38h
Command
10 11 12 13 14 15 16 17 18 19 20 21
Mode 3
Mode 0


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