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ISL6127IRZA Fiches technique(PDF) 9 Page - Intersil Corporation |
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ISL6127IRZA Fiches technique(HTML) 9 Page - Intersil Corporation |
9 / 16 page 9 FN9005.4 June 10, 2005 1. Using the ISL6123IR or ISL6124IR 2. The four supplies being sequenced are 5V (IN_A), 3.3V (IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels are ~ 80% of nominal voltages. Resistors chosen such that the total resistance of each divider is ~ 10K using standard value resistors to approximate 80% of nominal = 0.63V on UVLO input. 3. The desired order turn-on sequence is first both 5V and 3.3V supplies together and then the 2.5V supply about 75ms later and lastly the 1.5V supply about 45ms later. 4. The desired turn-off sequence is first both 1.5V and 3.3V supplies at the same time then the 2.5V supply about 50ms later and lastly the 5V supply about 72ms after that. All scope shots taken from ISL612xSEQEVAL1 board. Figures 7 and 8 illustrate the desired turn-on and turn-off sequences respectively. The sequencing order and delay between voltages sequencing is set by external capacitance values so other than illustrated can be accomplished. Figures 9 and 10 illustrate the timing relationships between the EN input, RESET#, DLY and GATE outputs and the VOUT voltage for a single channel being turned on and off respectively. RESET# is not shown in Figure 9 as it asserts 160ms after the last GATE goes high. All IC family variants share similar function for DLY_X capacitor charging, GATE and RESET# operation. Figures 11 through 14 illustrate the principal feature and functional differences for each of the ISL6125, ISL6126, ISL6127 and ISL6128 variants, each is described below. Figure 11 features the 6125 open drain outputs being sequenced on and off along with RESET# relatiionship which is similar to all other family variants. Figure 12 illustrates the independent input feature of the ISL6126 which allows once the EN# is low for each UVLO to be individually satisfied and for its associated GATE to turn- on. Only when the last variable VIN is satisfied as shown does the RESET# release to signal all input voltages are valid. Figure 13 shows the ISL6127 pre programmed ABCD on DCBA off order of sequencing with minimal non adjustable delay between each. Figure 14 demonstrates the independence of the redundant two rail sequencer. It shows that either one of the two groups can be turned off and the ABCD order of restart with capacitor programmable delay once both EN inputs are pulled low. Typical Performance Waveforms FIGURE 7. ISL6124 SEQUENCED TURN-ON FIGURE 8. ISL6124 SEQUENCED TURN-OFF 1V/DIV 40ms/DIV 5VOUT 3.3VOUT 2.5VOUT RESET# ENABLE# 1.5VOUT 1V/DIV 20ms/DIV 5VOUT 3.3VOUTPUT 2.5VOUT 1.5VOUT ENABLE# ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 |
Numéro de pièce similaire - ISL6127IRZA |
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Description similaire - ISL6127IRZA |
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