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ISL6123IR Fiches technique(PDF) 2 Page - Intersil Corporation |
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ISL6123IR Fiches technique(HTML) 2 Page - Intersil Corporation |
2 / 16 page 2 FN9005.4 June 10, 2005 Pinout ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 (QFN) TOP VIEW FIGURE 1. TYPICAL ISL6123 APPLICATION USAGE AOUT AIN BIN CIN DIN BOUT COUT DOUT UVLO_B UVLO_A UVLO_D UVLO_C ENABLE SYSRST# GROUND RESET# VDD 4mm X 4mm 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 78 9 10 11 12 Pin Descriptions PIN # PIN NAME FUNCTION DESCRIPTION 23 VDD Chip Bias Bias IC from nominal 1.5V to 5V 10 GND Bias Return IC ground 1 ENABLE_1/ ENABLE#_1 Input to start on/off sequencing. Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is disabled for 10ms after UVLO is satisfied. ISL6123 has ENABLE. ISL6124, ISL6125, ISL6126 and ISL6127 have ENABLE#. Only ISL6128 has 2 ENABLE# inputs, 1 for each 2 channel grouping. EN_1# for (A, B), and EN_2# for (C, D). 11 ENABLE#_2 24 RESET# RESET# Output RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for stabilization of output voltages. RESET# will assert low upon UVLO not being satisfied or ENABLE/ENABLE# being deasserted. The RESET outputs are open drain N channel FET and is guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X. RESET#_2 only exists on ISL6128 for (C, D) group I/O. 9 RESET#_2 20 UVLO_A Under Voltage Lock Out/Monitoring Input These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference and are filtered to ignore short (<30µs) transients below programmed UVLO level. 12 UVLO_B 17 UVLO_C 14 UVLO_D 21 DLY_ON_A Gate On Delay Timer Output Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current source providing delay to the associated FETs GATE turn-on. These pins are NC on ISL6126 and ISL6127 8DLY_ON_B 16 DLY_ON_C 15 DLY_ON_D 18 DLY_OFF_A Gate Off Delay Timer Output Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference voltage causing the corresponding gate to be pulled down turning-off the FET. These pins are NC on ISL6127 13 DLY_OFF_B 3 DLY_OFF_C 4 DLY_OFF_D ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 |
Numéro de pièce similaire - ISL6123IR |
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Description similaire - ISL6123IR |
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