11

Propagation Delay

The converter requires two clock rising edges for data to be

represented at the output. Each rising edge of the clock

captures the present data word and outputs the previous

data. The propagation delay is therefore 1/CLK, plus <2ns of

processing. See Figure 8.

Test Service

Intersil offers customer-specific testing of CommLink

converters with a service called Testdrive. To submit a

request, fill out the Testdrive form at

www.intersil.com/testdrive. Or, send a request to the

technical support center.

ISL5629

FIGURE 6. OUTPUT LOADING FOR DATASHEET

MEASUREMENTS

OUTA

OUTB

LOAD SEEN BY THE TRANSFORMER

1:1

AT EACH OUTPUT

FIGURE 7. ALTERNATIVE OUTPUT LOADING

ISL5629

OUTA

OUTB

AT EACH OUTPUT

LOAD SEEN BY THE TRANSFORMER

Timing Diagram

FIGURE 8. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

CLK

50%

D7-D0

ISL5629