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AD9992 Fiches technique(PDF) 2 Page - Analog Devices |
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AD9992 Fiches technique(HTML) 2 Page - Analog Devices |
2 / 92 page AD9992 Rev. C | Page 2 of 92 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 5 Timing Specifications .................................................................. 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 11 Equivalent Circuits ......................................................................... 12 Terminology .................................................................................... 13 System Overview ............................................................................ 14 High Speed Precision Timing Core........................................... 15 Horizontal Clamping and Blanking......................................... 19 Horizontal Timing Sequence Example.................................... 25 Vertical Timing Generation ...................................................... 26 Vertical Sequences (VSEQ) ....................................................... 29 Vertical Timing Example........................................................... 45 Shutter Timing Control ............................................................. 47 Substrate Clock Operation (SUBCK) ...................................... 47 Field Counters............................................................................. 50 General-Purpose Outputs (GPOs) .......................................... 51 GP Look-Up Tables (LUT)........................................................ 55 Complete Exposure/Readout Operation Using Primary Counter and GPO Signals ......................................................... 56 Manual Shutter Operation Using Enhanced SYNC Modes.. 58 Analog Front End Description and Operation ...................... 62 Power-Up Sequence for Master Mode..................................... 64 Standby Mode Operation .......................................................... 67 CLI Frequency Change.............................................................. 67 Circuit Layout Information........................................................... 69 Typical 3 V System ..................................................................... 69 Typical 1.8 V System .................................................................. 69 External Crystal Application .................................................... 69 Serial Interface Timing .............................................................. 72 Layout of Internal Registers ...................................................... 73 Updating New Register Values ................................................. 74 Complete Register Listing ............................................................. 75 Outline Dimensions ....................................................................... 92 Ordering Guide .......................................................................... 92 REVISION HISTORY 10/07—Rev. B to Rev. C Changes to Vertical Timing Generation Section........................ 26 Changes to Vertical Sequences (VSEQ) Section......................... 29 Changes to Vertical Timing Example Section ............................ 45 Changes to Power-Up Sequence for Master Mode Section ...... 64 Changes to Figure 80...................................................................... 70 Changes to Figure 81...................................................................... 71 9/07—Rev. A to Rev. B Added Figure 2.................................................................................. 4 Deleted Endnote in Table 3 ............................................................. 5 Added Address 0x17 Bit 17 Information to Table 30................. 75 7/07—Rev. 0 to Rev. A Changes to Table 3 and Related Endnote .......................................5 Added Slave Mode and SHP/SHD Information to Table 4..........6 Changes to Table 5.............................................................................7 Changes to Table 7.............................................................................8 Changes to Figure 18...................................................................... 17 Changes to Figure 75...................................................................... 66 Changes to Figure 81...................................................................... 71 1/06—Revision 0: Initial Version |
Numéro de pièce similaire - AD9992_15 |
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Description similaire - AD9992_15 |
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