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AD9898 Fiches technique(PDF) 11 Page - Analog Devices

No de pièce AD9898
Description  CCD Signal Processor with Precision Timing Generator
Download  52 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9898 Fiches technique(HTML) 11 Page - Analog Devices

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AD9898
–11–
Table I. Control Register Address Map (Register Names Are Subject to Change)
Bit
Default
Register
Address
Content
Width
Value
Name
Register Description
0A
23
1
0
Unused
22
1
0
FDPOL
FD Polarity Control (0 = Low, 1 = High)
(21:16)
6
0x00
VSGMASK
VSG Masking (See Table XXIII)
(15:12)
4
0
SYNCCNT
External SYNC Setting
(VD
(11:10)
2
0
SVREP_MODE
Super Vertical Repetition Mode
SyncReg)
* 91
0
HBLKEXT
H Pulse Blanking Extend Control
81
0
HPULSECNT
H Pulse Control during Blanking
(7:4)
4
C
SPATLOGIC
SPAT Logic Setting (See Table XX)
(3:2)
2
3
SVOS
Second V Output Setting (10 = Output Repetition 1)
11
0
SPAT_EN
SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
01
0
MODE
Mode Control Bit (0 = Mode_A, 1 = Mode_B)
0B
(23:22)
2
0
Unused
21
1
1
SUBCK_EN
SUBCK Output Enable Control (0 = Disable, 1 = Enable)
20
1
1
VSG_EN
VSG Output Enable Control (0 = Disable, 1 = Enable)
(VD
(19:17)
3
0
Unused
SyncReg)
* 16
1
0
STROBE_EN
STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
15
1
0
Unused
(14:12)
3
0
SUBCKNUM_HP
High Precision Shutter SUBCLK Pulse Position/Number
11
1
0
Unused
(10:0)
11
0x7FF
SUBCKNUM
Total Number of SUBCKs per Field
0C
(23:21)
3
0
Unused
20
1
0
MSHUTINIT
MSHUT Initialize (1 = Forces MSHUT Low)
(19:18)
2
0
Unused
(VD
17
1
0
Unused
SyncReg)
* 16
1
0
MSHUTEN
MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)
15
1
0
Unused
(14:12)
3
0
MSHUTPOS_HP
MSHUT Position during High Precision Operation
11
1
0
Unused
(10:0)
11
0x000
MSHUTPOS
MSHUT Position during Normal Operation
0D
(23:17)
7
Unused
16
1
0
VSUBPOL
VSUB Active Polarity (0 = Low, 1 = High)
(VD
(15:11)
5
Unused
SyncReg)
* (10:0)
11
0x000
VSUBTOG
VSUB Toggle Position. Active starting line in any field.
0E
(23:21)
3
0
Unused
20
1
0
Unused. Test Mode. Should be set = 0.
(19:18)
2
0
Unused
(VD
17
1
0
Unused. Test Mode. Should be set = 0.
SyncReg)
* 16
1
0
Unused. Test Mode. Should be set = 0.
(15:10)
6
0x00
Unused
(9:0)
10
0x000
VGAGAIN
VGA Gain
D5
(23:4)
20
0x00000
Unused
31
1
DCLK2SEL
DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/
DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16)
21
0
DCLK1SEL
DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,
1 = Select CLI for DCLK1 Output)
(1:0)
2
0
CLKDIV
Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)
D6
(23:1)
23
0x000000
Unused
01
1
SLAVE_MODE
Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the
register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).


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