AD9444_15 datasheet(6/40 Pages) AD

No de pièce	AD9444

Description	14-Bit, 80 MSPS, A/D Converter

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Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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AD9444

Rev. 0 | Page 6 of 40

SWITCHING SPECIFICATIONS

AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.

Table 4.

AD9444BSVZ-80

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Full

VI

80

MSPS

Minimum Conversion Rate

Full

V

10

MSPS

CLK Period

Full

V

12.5

ns

CLK Pulse Width High1 (tCLKH)

Full

V

4

ns

CLK Pulse Width Low1 (tCLKL)

Full

V

4

ns

DATA OUTPUT PARAMETERS

Output Propagation Delay—CMOS (tPD)2 (DX, DCO+)

Full

IV

3

5.25

8

ns

Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+)

Full

VI

3

5

7.5

ns

Pipeline Delay (Latency)

Full

V

12

Cycles

Aperture Delay (tA)

Full

V

ns

Aperture Uncertainty (Jitter, tJ)

Full

V

0.2

ps rms

1 With duty cycle stabilizer (DCS) enabled.

2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.

3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.

N–12

N–11

N

N+1

AIN

CLK+

CLK–

DATA OUT

DCO+

DCO–

N

N+1

N–1

t

CLKH

t

CLKL

1/

fS

t

PD

12 CLOCK CYCLES

t

CPD

Figure 2. LVDS Mode Timing Diagram

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