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AD8381 Fiches technique(PDF) 7 Page - Analog Devices |
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AD8381 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 16 page REV. B AD8381 –7– –0.25% 10ns/DIV VIDx CL 150pF VMID = 7V VFS = 5V 0.25% 0.00% –0.50% –0.75% –1.00% 7V t = 0 TPC 7. Output Settling Time (Rising Edge) at CL, 5 V Step, INV = Low –0.25% 10ns/DIV VIDx CL 150pF VMID = 7V VFS = 5V 0.00% –0.50% –0.75% –1.00% 12V t = 0 TPC 8. Output Settling Time (Rising Edge) at CL, 5 V Step, INV = High 20ns/DIV 5V +30mV +20mV +10mV VMID = 7V –10mV –20mV VID5 VID0 – VID4 TPC 9. All-Hostile Crosstalk at CL 0.75% 10ns/DIV VIDx CL 150pF VMID = 7V VFS = 5V 1.00% 0.50% 0.25% 0.00% 2V –0.25% –0.50% –0.75% –1.00% t = 0 TPC 10. Output Settling Time (Falling Edge) at CL, 5 V Step, INV = Low 0.75% 10ns/DIV VIDx CL 150pF VMID = 7V VFS = 5V 1.00% 0.50% 0.25% 0.00% 7V t = 0 –0.25% –0.50% –0.75% TPC 11. Output Settling Time (Falling Edge) at CL, 5 V Step, INV = High 20ns/DIV +10mV VMID = 7V –10mV DB (0:9) TPC 12. Data Switching Transient (Feedthrough) at CL |
Numéro de pièce similaire - AD8381_15 |
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Description similaire - AD8381_15 |
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