Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

CDP1851CEX Fiches technique(PDF) 4 Page - Intersil Corporation

No de pièce CDP1851CEX
Description  CMOS Programmable I/O Interface
Download  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1851CEX Fiches technique(HTML) 4 Page - Intersil Corporation

  CDP1851CEX Datasheet HTML 1Page - Intersil Corporation CDP1851CEX Datasheet HTML 2Page - Intersil Corporation CDP1851CEX Datasheet HTML 3Page - Intersil Corporation CDP1851CEX Datasheet HTML 4Page - Intersil Corporation CDP1851CEX Datasheet HTML 5Page - Intersil Corporation CDP1851CEX Datasheet HTML 6Page - Intersil Corporation CDP1851CEX Datasheet HTML 7Page - Intersil Corporation CDP1851CEX Datasheet HTML 8Page - Intersil Corporation CDP1851CEX Datasheet HTML 9Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 14 page
background image
4-8
then executes an input or a load instruction, depending on the
mapping technique used. In either case the proper code must
be asserted on the RAO, RA1, and CS lines to read the buffer
register (see Table 6).
The INT line is deactivated on the leading edge of TPB. The
trailing edge of TPB sets the RDY line to signal the periph-
eral that the port is ready to be loaded with new data. If RDY
is low when the input mode is entered (i.e. after a reset), a
“dummy” read must be done to set RDY high and signal the
peripheral device that the port is ready to be loaded.
Output Mode
A peripheral STROBE pulse sent to the PlO generates an
interrupt to signal the CPU that the peripheral device is
ready for data. The CPU executes the proper output or store
instruction. Data are then read from memory and placed on
the bus. The data are latched into the port buffer at the end
of the window when RE/WE = 0 and WR/RE = 1. The RDY
line is also set at this time, indicating to the peripheral that
there is data in the port buffer. The INT line is deactivated at
the beginning of the window. After the peripheral reads valid
port data, it can send another STROBE pulse, clearing the
RDY line and activating the INT line as in the input mode.
Bidirectional Mode
This mode programs port A to function as both an input and
output port. The bidirectional feature allows the peripheral to
control port direction by using both sets of handshake signals.
The port A handshaking pins are used to control input data
from peripheral to PlO, while the port B handshaking pins are
used to control output data from PlO to peripheral. Data are
transferred in the same manner as the input and output
modes. Since A INT is used for both input and output, the sta-
tus register must be read to determine what condition caused
A INT to be activated (see Table 5).
Bit-Programmable Mode
This mode allows individual bits of port A or port B to be
programmed as inputs or outputs. To output data to bits
programmed as outputs, the CPU loads a data byte into the
8-bit port as in the output mode (no handshaking). Only bits
programmed for outputs latch this data. Data must be stable
when reading from bits programmed as inputs, since the
input bits do not latch. When the CDP1851 inputs data to the
CPU the CPU also reads the output bits latched during the
last output cycle. The RDY and STROBE lines may be used
for I/O by using the STROBE/RDY I/O control byte in Table 2.
An additional feature available in the bit-programmable
mode is the ability to generate interrupts based on
input/output byte combinations. These interrupts can be
programmed to occur on logic conditions (AND, OR, NAND,
and NOR) generated by the eight I/O lines of each port (The
STROBE and RDY lines cannot generate interrupts).
A0
A1
A2
A3
A4
A5
A6
A7
INT
BUS 0-7
CDP1800
FAMILY
µP
TPA
MWR
MRD
TPB
VDD
10k
RA0
RA1
A RDY
PORT A0 - A7
PORT B0 - B7
A INT
BUS 0-7
PIO
NO. 1
CLOCK
RD/WE
WR/RE
TPB
CDP1851
B INT
CS
B RDY
A STROBE
B STROBE
RA0
RA1
A RDY
PORT A0 - A7
PORT B0 - B7
PIO
NO. 2
CLOCK
RD/WE
WR/RE
TPB
CDP1851
B RDY
A STROBE
B STROBE
CS
A INT
B INT
ADDRESS REGISTER
ADDRESS
SELECTS
8001
No. 1 Control/Status Reg
8002
No. 1 Port A
8003
No. 1 Port B
8004
No. 2 Control/Status Reg
8008
No. 2 Port A
800C
No. 2 Port B
FIGURE 2. MEMORY SPACE I/O. THIS CONFIGURATION ALLOWS UP TO FOUR CDP1851s TO OCCUPY MEMORY SPACE 8XXX WITH
NO ADDITIONAL HARDWARE (A4-A5 AND A6-A7 ARE USED AS RA0 AND RA1 ON THE THIRD AND FOURTH PIO’s)
CDP1851, CDP1851C


Numéro de pièce similaire - CDP1851CEX

FabricantNo de pièceFiches techniqueDescription
logo
Intersil Corporation
CDP1852 INTERSIL-CDP1852 Datasheet
153Kb / 9P
   Byte-Wide Input/Output Port
March 1997
CDP1852/3 INTERSIL-CDP1852/3 Datasheet
218Kb / 7P
   High-Reliability Byte-Wide Input/Output Port
CDP18523 INTERSIL-CDP18523 Datasheet
218Kb / 7P
   High-Reliability Byte-Wide Input/Output Port
CDP1852C INTERSIL-CDP1852C Datasheet
153Kb / 9P
   Byte-Wide Input/Output Port
March 1997
CDP1852C/3 INTERSIL-CDP1852C/3 Datasheet
218Kb / 7P
   High-Reliability Byte-Wide Input/Output Port
More results

Description similaire - CDP1851CEX

FabricantNo de pièceFiches techniqueDescription
logo
IC-Haus GmbH
IC-GD ICHAUS-IC-GD Datasheet
1,023Kb / 55P
   UNIVERSAL I/O INTERFACE
logo
Toshiba Semiconductor
TLP181GB-TPLFT TOSHIBA-TLP181GB-TPLFT Datasheet
209Kb / 9P
   Office Machine Programmable Controllers AC Adapter I/O Interface Board
TLP181F TOSHIBA-TLP181F Datasheet
209Kb / 9P
   Office Machine Programmable Controllers AC Adapter I/O Interface Board
TLP181T TOSHIBA-TLP181T Datasheet
209Kb / 9P
   Office Machine Programmable Controllers AC Adapter I/O Interface Board
TLP185GB-TPLEO TOSHIBA-TLP185GB-TPLEO Datasheet
239Kb / 11P
   Office Machine Programmable Controllers AC Adapter I/O Interface Board
TLP-181 TOSHIBA-TLP-181 Datasheet
217Kb / 9P
   Office Machine Programmable Controllers AC Adapter I/O Interface Board
logo
SPANSION
S25FL128SAGMFI001 SPANSION-S25FL128SAGMFI001 Datasheet
5Mb / 153P
   CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O
logo
Toshiba Semiconductor
TMP82C255A TOSHIBA-TMP82C255A Datasheet
682Kb / 32P
   CMOS PROGRAMMABLE PERIPHERAL INTERFACE
TMP82C265BF TOSHIBA-TMP82C265BF Datasheet
1Mb / 31P
   CMOS PROGRAMMABLE PERIHERAL INTERFACE
logo
Intersil Corporation
CS82C55AZ96 INTERSIL-CS82C55AZ96 Datasheet
560Kb / 29P
   CMOS Programmable Peripheral Interface
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com