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CDP1824CE Fiches technique(PDF) 1 Page - Intersil Corporation

No de pièce CDP1824CE
Description  32-Word x 8-Bit Static RAM
Download  6 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP1824CE Fiches technique(HTML) 1 Page - Intersil Corporation

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Features
• Fast Access Time
-VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns
-VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns
• No Precharge or Clock Required
Description
The CDP1824 and CDP1824C are 32-word x 8-bit fully static
CMOS random-access memories for use in CDP-1800
series microprocessor systems. These parts are compatible
with the CDP1802 microprocessor and will interface directly
without additional components.
The CDP1824 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has
common input and output and is operated from a single
voltage supply. The MRD signal (output disable control)
enables the three-state output drivers, and overrides the
MWR signal. A CS input is provided for memory expansion.
The CDP1824C is functionally identical to the CDP1824.
The CDP1824 has an operating range of 4V to 10.5V, and
the CDP1824C has an operating voltage range of 4V to
6.5V. The CDP1824 and CDP1824C are supplied in 18 lead
hermetic dual-in-line ceramic packages (D suffix), and in 18
lead dual-in-line plastic packages (E suffix).
Pinout
CDP1824, CDP1824C (PDIP, SBDIP)
TOP VIEW
Ordering Information
5V
10V
PACKAGE
TEMPERATURE RANGE
PKG. NO.
CDP1824CE
CDP1824E
PDIP
-40oC to +85oC
E18.3
CDP1824CEX
CDP1824EX
Burn-In
E18.3
CDP1824CD
CDP1824D
SBDIP
-40oC to +85oC
D18.3
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VDD
MRD
CS
BUS 0
BUS 1
BUS 2
BUS 3
MWR
BUS 4
MA4
MA3
MA2
MA1
MA0
BUS 7
BUS 5
BUS 6
VSS
OPERATIONAL MODES
FUNCTION
CS
MRD MWR
DATA PINS STATUS
READ
0
0
X
Output: High/Low Dependent
on Data
WRITE
0
1
0
Input: Output Disabled
Not
Selected
1
X
X
Output Disabled:
High-Impedance State
Standby
0
1
1
Output Disabled:
High-Impedance State
Logic 1 = High
Logic 0 = Low
X = Don’t Care
March 1997
CDP1824,
CDP1824C
32-Word x 8-Bit Static RAM
File Number
1103.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright
© Intersil Corporation 1999


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