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CD4030 Fiches technique(PDF) 5 Page - Intersil Corporation

No de pièce CD4030
Description  CMOS Quad Exclusive-OR Gate
Download  7 Pages
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Fabricant  INTERSIL [Intersil Corporation]
Site Internet  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4030 Fiches technique(HTML) 5 Page - Intersil Corporation

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Specifications CD4030BMS
FIGURE 1. 1 OF 4 IDENTICAL GATES
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
MIL-STD-883
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
3, 4, 10, 11
1, 2, 5 - 9, 12, 13
14
Static Burn-In 2
Note 1
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
Dynamic Burn-
In Note 1
-
7
14
3, 4, 10, 11
2, 6, 9, 13
1, 5, 8, 12
Irradiation
Note 2
3, 4, 10, 11
7
1, 2, 5, 6, 8, 9,
12 - 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V
± 0.5V
Schematic Diagram
TABLE 6. APPLICABLE SUBGROUPS
(Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
B
*
2(5, 9, 12)
p
n
n
p
n
p
n
J
p
VDD
VSS
A
*
n
p
VDD
VSS
1(6, 8, 13)
p
3(4, 10, 11)
VSS
VDD
VDD
VSS
*INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
TRUTH TABLE FOR 1 OF 4
INDENTICAL GATES
AB
J
000
101
011
110
1 = High Level
0 = Low Level


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