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AD7711A Fiches technique(PDF) 3 Page - Analog Devices

No de pièce AD7711A
Description  LC MOS Signal Conditioning ADC
Download  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD7711A Fiches technique(HTML) 3 Page - Analog Devices

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Parameter
A, S Versions
1
Unit
Conditions/Comments
VBIAS INPUT
12
Input Voltage Range
AVDD – 0.85
¥ VREF
See VBIAS Input Section
or AVDD – 3.5
V max
Whichever Is Smaller: +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
or AVDD – 2.1
V max
Whichever Is Smaller: +5 V/0 V Nominal AVDD/VSS
VSS + 0.85
¥ VREF
See VBIAS Input Section
or VSS + 3
V min
Whichever Is Greater: +5 V/–5 V or +10 V/0 V
Nominal AVDD/VSS
or VSS + 2.1
V min
Whichever Is Greater: +5 V/0 V Nominal AVDD/VSS
VBIAS Rejection
65 to 85
dB typ
Increasing with Gain
LOGIC INPUTS
Input Current
±10
mA max
All Inputs except MCLK IN
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
2.0
V min
MCLK IN Only
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
3.5
V min
LOGIC OUTPUTS
VOL, Output Low Voltage
0.4
V max
ISINK = 1.6 mA
VOH, Output High Voltage
DVDD – 1
V min
ISOURCE = 100
mA
Floating State Leakage Current
±10
mA max
Floating State Output Capacitance
13
9
pF typ
TRANSDUCER BURNOUT
Current
4.5
mA nom
Initial Tolerance @ 25
∞C
±10
% typ
Drift
0.1
%/
∞C typ
RTD EXCITATION CURRENT
Output Current
400
mA nom
Initial Tolerance @ 25
∞C
±20
% max
Drift
20
ppm/
∞C typ
Line Regulation (AVDD)
400
nA/V max
AVDD = 5 V
Load Regulation
400
nA/V max
Output Compliance
AVDD – 2
V max
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
(1.05
¥ VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit
14
–(1.05
¥ VREF)/GAIN V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit
15
–(1.05
¥ VREF)/GAIN V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span
15
0.8
¥ VREF/GAIN
V min
GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1
¥ VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12The AD7711A is tested with the following V
BIAS voltages. With AVDD = 5 V and VSS = 0 V, VBIAS = 2.5 V, with AVDD = 10 V and VSS = 0 V, VBIAS = 5 V, and with
AVDD = 5 V and VSS = –5 V, VBIAS = 0 V.
13Guaranteed by design, not production tested.
14After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD + 30 mV or go more negative than V SS – 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
AD7711A
–3–
REV. D


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