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8XC251SA Fiches technique(PDF) 17 Page - Intel Corporation

No de pièce 8XC251SA
Description  HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Download  36 Pages
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Fabricant  INTEL [Intel Corporation]
Site Internet  http://www.intel.com
Logo INTEL - Intel Corporation

8XC251SA Fiches technique(HTML) 17 Page - Intel Corporation

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PRELIMINARY
17
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
V
OH
1
Output High Voltage
(Port 0 in External
Address)
V
CC – 0.3
V
CC – 0.7
V
CC – 1.5
VI
OH = -200 µA
I
OH = -3.2 mA
I
OH = -7.0 mA
V
OH
2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC – 0.3
VCC – 0.7
VCC – 1.5
VIOH = -200 µA
IOH = -3.2 mA
IOH = -7.0 mA
I
IL
Logical 0 Input Cur-
rent (Port 1, 2, 3)
-50
µA
VIN = 0.45 V
I
LI
Input Leakage Cur-
rent (Port 0)
+/-10
µA
0.45 < VIN < V
CC
I
TL
Logical 1-to-0 Transi-
tion Current (Port 1,
2, 3)
-650
µA
VIN = 2.0 V
R
RST
RST Pulldown Resis-
tor
40
225
k
C
IO
Pin Capacitance
10
(Note 4)
pF
F
OSC = 16 MHz
TA = 25 °C
I
PD
Powerdown Current
10
(Note 4)
20
µA
I
DL
Idle Mode Current
12
(Note 4)
15
mA
F
OSC = 16 MHz
I
CC
Operating Current
45
(Note 4)
80
mA
F
OSC = 16 MHz
Table 9. DC Characteristics at V
CC = 4.5 – 5.5 V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
NOTES:
1.
Under steady-state (non-transient) conditions, I
OL must be externally limited as follows:
Maximum I
OL per port pin:
10 mA
Maximum I
OL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total I
OL for
all output pins
71 mA
If I
OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2.
Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3.
Capacitive loading on ports 0 and 2 causes the V
OH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4.
Typical values are obtained using V
CC = 5.0, TA = 25°C and are not guaranteed.


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