AD1376/AD1377

Rev. D | Page 9 of 12

Table 5. Transition Values vs. Calibration Codes

Output Code

MSB

LSB1

Range

±10 V

±5 V

±2.5 V

0 V to +10 V

0 V to +5 V

000 ………0002

+Full Scale

+10 V

+5 V

+2.5 V

+10 V

+5 V

−3/2 LSB

−3/2 LSB

−3/2 LSB

−3/2 LSB

−3/2 LSB

011………111

Midscale

0 V

0 V

0 V

+5 V

+2.5 V

–1/2 LSB

–1/2 LSB

–1/2 LSB

–1/2 LSB

–1/2 LSB

111………110

−Full Scale

−10 V

−5 V

−2.5 V

0 V

0 V

+1/2 LSB

+1/2 LSB

+1/2 LSB

+1/2 LSB

+1/2 LSB

.

ble 6

Table 6. Input Voltage Range and LSB Values

Analog Input Voltage Range

±10 V

±5 V

±2.5 V

0 V to +10 V

0 V to +5 V

Code Designation

COB1 or CTC2

COB1 or CTC2

COB1 or CTC2

CSB3

CSB3

One Least Significant Bit (LSB)

n

2

FSR

n

2

V

20

n

2

V

10

n

2

V

5

n

2

V

10

n

2

V

5

n = 8

78.13 mV

39.06 mV

19.53 mV

39.06 mV

19.53 mV

n = 10

19.53 mV

9.77 mV

4.88 mV

9.77 mV

4.88 mV

n = 12

4.88 mV

2.44 mV

1.22 mV

2.44 mV

1.22 mV

n = 13

2.44 mV

1.22 mV

0.61 mV

1.22 mV

0.61 mV

n = 14

1.22 mV

0.61 mV

0.31 mV

0.61 mV

0.31 mV

n = 15

0.61 mV

0.31 mV

0.15 mV

0.31 mV

0.15 mV

Zero- and full-scale calibration can be accomplished to a

precision of approximately ±1/2 LSB using the static adjustment

procedure described previously. By summing a small sine or

triangular wave voltage with the signal applied to the analog

input, the output can be cycled through each of the calibration

codes of interest to more accurately determine the center (or

end points) of each discrete quantization level. A detailed

description of this dynamic calibration technique is presented

in Analog-Digital Conversion Handbook, edited by D. H.

Sheingold, Prentice Hall, Inc., 1986.

GROUNDING, DECOUPLING, AND LAYOUT

CONSIDERATIONS

Many data acquisition components have two or more ground

pins that are not connected together within the device. These

grounds are usually referred to as DIGITAL COMMON (logic

power return), ANALOG COMMON (analog power return), or

analog signal ground. These grounds (Pin 19 and Pin 22) must

be tied together at one point as close as possible to the

converter. Ideally, a single solid analog ground plane under the

converter would be desirable. Current flows through the wires

and etch stripes of the circuit cards, and since these paths have

resistance and inductance, hundreds of millivolts can be

generated between the system analog ground point and the

ground pins of the ADC. Separate wide conductor stripe

ground returns should be provided for high resolution

converters to minimize noise and IR losses from the current

flow in the path from the converter to the system ground point.

In this way, ADC supply currents and other digital logic-gate

return currents are not summed into the same return path as

analog signals where they would cause measurement errors.

Each of the ADC supply terminals should be capacitively

decoupled as close to the ADC as possible. A large value (such

as 1 µF) capacitor in parallel with a 0.1 µF capacitor is usually

sufficient. Analog supplies are to be bypassed to the ANALOG

COMMON (analog power return) Pin 22 and the logic supply is

bypassed to DIGITAL COMMON (logic power return) Pin 19.

The metal cover is internally grounded with respect to the

power supplies, grounds, and electrical signals. Do not

externally ground the cover.

CLOCK RATE CONTROL

The AD1376/AD1377 can be operated at faster conversion

times by connecting the clock rate control (Pin 23) to an

external multiturn trim potentiometer (TCR <100 ppm/°C) as

shown in Figure 13.

AD1376/AD1377

23

2.25MHz @ 5V

1750kHz @ DGND

15V DC

5k

Ω

Figure 13. Clock Rate Control Circuit