IDT71B74

BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM

COMMERCIAL TEMPERATURE RANGE

14.1

4

NOTES:

1. For more information refer to IDT Application Notes AN-07 and AN-78 and Technical Notes TN-11 and TN-13.

Ω.

Figure 4. Example of Cache Memory System Block Diagram

3013 drw 05

480

Ω

5pF*

255

Ω

5V

Figure 1A. Lumped Capacitive Load

Typical Derating Curve

1

2

3

4

5

6

7

20 40

60 80 100 120 140 160 180 200

∆TADM

(Typical, ns)

CAPACITANCE (pF)

8

3013 drw 04

•

•

•

•

•

•

•

*Includes scope and jig.

Figure 2. AC Test Load

1

2

3

4

5

6

7

20 40 60 80 100 120 140 160 180 200

∆TAA

(Typical, ns)

CAPACITANCE (pF)

8

3013 drw 07

•

•

•

•

•

•

•

3013 drw 06

MATCH

5V

Ω (COM’L.)

= 270

Ω (MIL.)

Figure 3. AC Test Load for MATCH

Figure 3A. Lumped Capacitive Load

Typical Derating Curve

80486

32-BIT

MICROPROCESSOR

3013 drw 08

RDY

CLEAR

5V

(2)

MEMORY READ/WRITE

CONTROL LOGIC

CACHE READ/WRITE

MAIN MEMORY READ/WRITE

ADDR

DATA

MAIN

MEMORY

ADDR

DATA

LOGIC 1

IDT71256

CACHE-

DATA

RAM

IDT71B74

CACHE-

TAG

RAM

MATCH

IDT71B74

CACHE-

TAG

RAM

MATCH

8

9

8

9

8

8

87

13

32

32

256

256

256