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HMS87C1304A Fiches technique(PDF) 58 Page - Hynix Semiconductor |
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HMS87C1304A Fiches technique(HTML) 58 Page - Hynix Semiconductor |
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58 / 88 page  HMS87C130XA/120XA/110XA Apr. 2001 ver1.0 55 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 15-2. These registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corre- sponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers When an interrupt is occurred, the I-flag is cleared and dis- able any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. The interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. The Interrupt Request flags are able to be read and written. Reset/Interrupt Symbol Priority Vector Addr. Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 A/D Converter Watch Dog Timer Basic Interval Timer RESET INT0 INT1 Timer 0 Timer 1 A/D C WDT BIT - 1 2 3 4 5 6 7 FFFEH FFFAH FFF8H FFF6H FFF4H FFEAH FFE8H FFE6H Table 15-1 Interrupt Priority IENH ADDRESS : E2H RESET VALUE : 0000---- INT0E INT1E T0E T1E - - - - Interrupt Enable Register High IENL ADDRESS : E3H RESET VALUE : 000----- ADE WDTE BITE - - - - - Interrupt Enable Register Low IRQH ADDRESS : E4H RESET VALUE : 0000---- INT0IF INT1IF T0IF T1IF - - - - Interrupt Request Register High IRQL ADDRESS : E5H RESET VALUE : 000----- ADIF WDTIF BITIF - - - - - Interrupt Request Register Low 0 : Disable 1 : Enable Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Not occurred 1 : Interrupt request is occurred Shows the interrupt occurrence |
Numéro de pièce similaire - HMS87C1304A |
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Description similaire - HMS87C1304A |
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