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HD74HC299 Fiches technique(PDF) 2 Page - Hitachi Semiconductor |
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HD74HC299 Fiches technique(HTML) 2 Page - Hitachi Semiconductor |
2 / 11 page HD74HC299 2 Function Table Inputs Function Select Output Control Serial Inputs/Outputs Outputs Mode Clear S 1 S 0 G 1† G 2† Clock S L S R A/Q A B/Q B C/Q C D/Q D E/Q E F/Q F G/Q G H/QH Q A’QH’ Clear L X L L L X X X L L L L L L L L L L L L X L L X X X L L L L LLL LL L Hold H LLLL X X X Q A0 Q B0 Q C0 Q D0 Q E0 Q F0 Q G0 Q H0 Q A0 Q H0 H XXL L L X X Q A0 Q B0 Q C0 Q D0 Q E0 Q F0 Q G0 Q H0 Q A0 Q H0 Shift H L H L L XH H Q An Q Bn Q Cn Q Dn Q En Q Fn Q Gn HQ Gn Right H L H L L XL L Q An Q Bn Q Cn Q Dn Q En Q Fn Q Gn LQ Gn Shift H H L L L HX Q Bn Q Cn Q Dn Q En Q Fn Q Gn Q Hn HQ Bn H Left H H L L L LX Q Bn Q Cn Q Dn Q En Q Fn Q Gn Q Hn LQ Bn L Load H H H X X X X a bc de f g h a h Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flip-flop outputs are isolated from the input/output terminals. 2. Q A0 to QH0; the level of QA through QH, respectively, before the indicated steady-state input conditions were established. 3. Q An to QHn; the level of QA through QH, respectively, before the most-recent transition of the clock. 4. † = ; When one or both output controls are high the eight input/output terminals are desabled to the high-impedance state, however, sequential operation or clearing of the register is not affected. 5. When clear is low, outputs of Q A’ and QH’ are low, in spite of other inputs. |
Numéro de pièce similaire - HD74HC299 |
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Description similaire - HD74HC299 |
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