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ADC08500CIYB Fiches technique(PDF) 4 Page - Texas Instruments |
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ADC08500CIYB Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 46 page GND VA 50k 50k GND VA 50k 50k 200k 8 pF GND VA GND VA 50k 50k 200k 8 pF VA SDATA DDR GND VA 50k ADC08500 SNAS373E – MAY 2007 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this pin for a reduced differential output amplitude and reduced power consumption. See The LVDS Outputs. When 3 OutV / SCLK the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. DCLK Edge Select, Double Data Rate Enable and Serial Data Input. This input sets the output edge of DCLK+ at which the output data transitions. When this pin is floating or connected to OutEdge / DDR / 1/2 the supply voltage, DDR clocking is enabled. See Double 4 SDATA Data Rate. When the extended control mode is enabled, this pin functions as the SDATA input. See NORMAL/EXTENDED CONTROL for details on the extended control mode. See THE SERIAL INTERFACE for description of the serial interface. DCLK Reset. A positive pulse on this pin is used to reset and 15 DCLK_RST synchronize the DCLK outs of multiple converters. See MULTIPLE ADC SYNCHRONIZATION for detailed description. Power Down Pin. A logic high on the PD pin puts the entire 26 PD device into the Power Down Mode. Calibration Cycle Initiate. A minimum tCAL_L input clock cycles logic low followed by a minimum of tCAL_H input clock cycles 30 CAL high on this pin initiates the self calibration sequence. See Self Calibration for an overview of self-calibration and On-Command Calibration for a description of on-command calibration. Full Scale Range Select and Extended Control Enable. In non- extended control mode, a logic low on this pin sets the full-scale differential input range to a reduced VIN input level . A logic high on this pin sets the full-scale differential input range to a higher VIN input level. See Converter Electrical Characteristics. To 14 FSR/ECE enable the extended control mode, whereby the serial interface and control registers are employed, allow this pin to float or connect it to a voltage equal to VA/2. See NORMAL/EXTENDED CONTROL for information on the extended control mode. Calibration Delay and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of clock cycles after power up before 127 CalDly / SCS calibration begins. See Self-Calibration. With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no provision for a long power-up calibration delay). 4 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: ADC08500 |
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