ADC10065

www.ti.com

SNAS225H – JULY 2003 – REVISED APRIL 2013

OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10

0000 0000.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. Data for any given sample is available at the output pins the

Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle,

but the data lags the conversion by the pipeline delay.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency,

including harmonics but excluding DC.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output

spectrum that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as:

White Space

where

•

•

(2)

SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power

in the input frequency at the output and the power in its 2nd harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in

the input frequency at the output and the power in its 3rd harmonic level at the output.

Copyright © 2003–2013, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Links: ADC10065