Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

TLC3545 Fiches technique(PDF) 3 Page - Texas Instruments

Click here to check the latest version.
No de pièce TLC3545
Description  200-KSPS Sampling Rate Built-In Conversion Clock
Download  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TLC3545 Fiches technique(HTML) 3 Page - Texas Instruments

  TLC3545 Datasheet HTML 1Page - Texas Instruments TLC3545 Datasheet HTML 2Page - Texas Instruments TLC3545 Datasheet HTML 3Page - Texas Instruments TLC3545 Datasheet HTML 4Page - Texas Instruments TLC3545 Datasheet HTML 5Page - Texas Instruments TLC3545 Datasheet HTML 6Page - Texas Instruments TLC3545 Datasheet HTML 7Page - Texas Instruments TLC3545 Datasheet HTML 8Page - Texas Instruments TLC3545 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 27 page
background image
TLC3541, TLC3545
SLAS345 − DECEMBER 2001
3
www.ti.com
Terminal Functions
TLC3541 single channel unipolar ADCs
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN
4
I
Analog input channel
CS
1
I
Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a
maximum delay time. If the TLC3541 is attached to a dedicated TMS320 DSP serial port using the FS input,
CS can be grounded.
FS
7
I
DSP frame sync input. Indication of a start of a serial data frame. A low-to-high transition removes SDO from
the high-impedance state and the MSB is presented. Tie this pin to VDD if not used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
SDO
8
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high. The output format is MSB first. Remaining data bits are presented on the rising edge of SCLK.
When FS is not active (FS = 1 at the falling edge of CS): The MSB is presented on the SDO pin on the falling
edge of CS after a maximum delay time. Data is valid on each falling edge of SCLK until all data is read.
When FS is active (FS = 0 at the falling edge of CS): The MSB is presented to the SDO output on the rising
edge of FS. Data is valid on the falling edge SCLK and changes on the rising edge SCLK (this is typically
used with an active FS from a DSP).
SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not
presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising
edge of CS.
SCLK
5
I
Serial clock. This terminal receives the serial SCLK from the host processor.
REF
2
I
External voltage reference input
VDD
6
I
Positive supply voltage
TLC3545 single channel pseudo-differential ADCs
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AIN0 (+)
4
I
Positive analog input for the TLC3545.
AIN1 (−)
5
I
Inverted analog input for the TLC3545.
CS
1
I
Chip select. A high-to-low transition on CS removes SDO from the high-impedance state within a maximum
delay time. The CS input can be connected to a DSP frame sync (FS) output when a dedicated TMS320 DSP
serial port is used.
GND
3
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
SDO
8
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is
MSB first. The remaining data bits are presented on the rising edge of SCLK. Output data is valid on each
falling edge of SCLK until all data is read. SDO returns to the high-impedance state after the 17th rising edge
on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the
high-impedance state on the rising edge of CS.
SCLK
7
I
Serial clock. This terminal receives the serial SCLK from the host processor.
REF
2
I
External voltage reference input
VDD
6
I
Positive supply voltage


Numéro de pièce similaire - TLC3545

FabricantNo de pièceFiches techniqueDescription
logo
Texas Instruments
TLC3545 TI-TLC3545 Datasheet
481Kb / 23P
[Old version datasheet]   5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN
TLC3545ID TI-TLC3545ID Datasheet
481Kb / 23P
[Old version datasheet]   5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN
TLC3545IDGK TI-TLC3545IDGK Datasheet
481Kb / 23P
[Old version datasheet]   5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN
TLC3545IDGKR TI-TLC3545IDGKR Datasheet
481Kb / 23P
[Old version datasheet]   5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN
TLC3545IDGKRG4 TI-TLC3545IDGKRG4 Datasheet
481Kb / 23P
[Old version datasheet]   5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN
More results

Description similaire - TLC3545

FabricantNo de pièceFiches techniqueDescription
logo
Texas Instruments
TLV1504 TI1-TLV1504_14 Datasheet
1Mb / 48P
[Old version datasheet]    Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO
TLV2544 TI1-TLV2544_14 Datasheet
1Mb / 48P
[Old version datasheet]   Maximum Throughput 200-KSPS Built-In Reference, Conversion Clock and 8횞 FIFO
logo
Analog Devices
AD678 AD-AD678_15 Datasheet
305Kb / 14P
   12-Bit 200 kSPS Complete Sampling ADC
REV. C
AD678 AD-AD678 Datasheet
311Kb / 14P
   12-Bit 200 kSPS Complete Sampling ADC
REV. C
logo
Texas Instruments
ADC122S655 TI1-ADC122S655_15 Datasheet
1Mb / 28P
[Old version datasheet]   Dual 12-Bit, 200 kSPS to 500 kSPS, Simultaneous Sampling A/D Converter
ADC122S625 TI1-ADC122S625_15 Datasheet
1Mb / 28P
[Old version datasheet]   Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter
logo
National Semiconductor ...
ADC122S625 NSC-ADC122S625 Datasheet
496Kb / 20P
   Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter
ADC122S655 NSC-ADC122S655 Datasheet
498Kb / 20P
   Dual 12-Bit, 200 kSPS to 500 kSPS, Simultaneous Sampling A/D Converter
logo
Texas Instruments
ADC122S655 TI1-ADC122S655_14 Datasheet
1Mb / 28P
[Old version datasheet]   ADC122S655 Dual 12-Bit, 200 kSPS to 500 kSPS, Simultaneous Sampling A/D Converter
ADC122S625 TI1-ADC122S625_14 Datasheet
1Mb / 28P
[Old version datasheet]   ADC122S625 Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com