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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS23751 Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS23751 Fiches technique(HTML) 11 Page - Texas Instruments |
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11 / 47 page  1 SLPb MPS MODE Oscillator 1 Sleep Frequency Divider Soft Start Complete Sleep MPS VB WAKE Sleep APD MPS + Sleep VREF LED VC ARTN VB Sleep Sleep MPS Regulator D CLR CLK Q Q D CLR CLK Q Q D CLR CLK Q Q TPS23751 TPS23752 www.ti.com SLVSB97A – JULY 2012 – REVISED AUGUST 2012 SLEEP MODE FUNCTIONALITY (TPS23752 ONLY) PIN DESCRIPTION The following descriptions refer to the schematic of Figure 1 and the Functional Block Diagrams. APD: (Auxiliary Power Detect): The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary power source. A voltage of more than about 1.5 V on the APD pin relative to RTN turns off the internal pass MOSFET, disables the CLS output, and enables the T2P output. A resistor divider (RAPD1–RAPD2 in Figure 1) provides system-level ESD protection for the APD pin, discharges leakage from the blocking diode (DA in Figure 1), and provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at excessively low voltages. If not used, connect APD to ARTN. When the TPS23752 operates in Sleep Mode, holding APD higher than its rising threshold, VAPDEN, disables the maintain power signature (MPS). ARTN: The ARTN pin is the local ground return for the DC-DC controller. Connections to the ARTN pin should return to a local ground plane beneath the DC-DC converter primary circuitry. For most applications, this ground plane should also connect to RTN. CLS: An external resistor (RCLS in Figure 1) connected between the CLS pin and VSS provides a classification signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor whenever the voltage differential between VDD and VSS lies between about 10.9 V and 22 V. The current drawn by this resistor, combined with the internal current drain of the controller and any leakage through the internal pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, including all losses within the DC-DC converter as well as power supplied to the downstream load, should not exceed the maximum power indicated in Table 1. Holding APD high disables the classification signature. High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS23751 TPS23752 |
Numéro de pièce similaire - TPS23751_14 |
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Description similaire - TPS23751_14 |
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