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FIN1216 Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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FIN1216 Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 20 page September 2009 © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Low Power Consumption 20MHz to 85MHz Shift Clock Support 50% Duty Cycle on the Clock Output of Receiver ±1V Common-mode Range ~1.2V Narrow Bus Reduces Cable Size and Cost High Throughput: 1.785Gbps Up to 595Mbps per Channel Internal PLL with No External Components Compatible with TIA/EIA-644 Specification Offered in 48-lead TSSOP Packages Description The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low-Voltage TTL) data into three serial LVDS (Low-Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted. The FIN1216 and FIN1218 receives and converts the three serial LVDS data streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the FIN1217, at a transmit clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Part Number Operating Temperature Range Eco Status Package Packing Method FIN1215MTDX -40 to + 85°C RoHS 48-Lead Thin Shrink Small Outline Package (TSSOP) Tape and Reel FIN1216MTDX FIN1217MTDX FIN1218MTDX (Preliminary) For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. |
Numéro de pièce similaire - FIN1216 |
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Description similaire - FIN1216 |
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