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UC2849DW Fiches technique(PDF) 6 Page - Texas Instruments

No de pièce UC2849DW
Description  SECONDARY SIDE AVERAGE CURRENT MODE CONTROLLER
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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Pin Descriptions
Frequency [
1
T
CHARGE ) TDISCHARGE
(1)
Maximum Duty Cycle [
T
CHARGE
T
CHARGE ) TDISCHARGE
(2)
UC2849
UC3849
SLUS360C – JULY 1995 – REVISED AUGUST 2007
ADJ: The output of the transconductance (gm = –1 ms) amplifier adjusts the control voltage to maintain equal
current sharing. The chip sensing the highest output current will have its output clamped to 1 V. A resistor
divider between VREF and ADJ drives the control voltage (VA+) for the voltage amplifier. Each slave unit's ADJ
voltage increases (to a maximum of 6 V) its control voltage (VA+) until its load current is equal to the master.
The 60-mV input offset on the gm amplifier specifies that the unit sensing the highest load current is chosen as
the master. The 60-mV offset ensures by design to be greater than the inherent offset of the gm amplifier and
the buffer amplifier. While the 60-mV offset represents an error in current sharing, the gain of the current and 2X
amplifiers reduces it to only 30 mV. This pin needs a 1-
μF capacitor to compensate the amplifier.to the master.
CA–: The inverting input to the current error amplifier. This amplifier needs a capacitor between CA– and CAO
to set its dominant pole.
CAO: The output of the current error amplifier which is internally clamped to 4 V. It is internally connected to the
inverting input of the PWM comparator.
CS–, CS+: The inverting and non-inverting inputs to the current sense amplifier. This amplifier is not internally
compensated so the user must compensate externally to attain the highest GBW for the application.
CLKSYN: The clock and synchronization pin for the oscillator. This is a bidirectional pin that can be used to
synchronize several chips to the fastest oscillator. Its input synchronization threshold is 1.4 V. The CLKSYN
voltage is 3.6 V when the oscillator capacitor (CT) is being discharged, otherwise it is 0 V. If the recommended
synchronization circuit is not used, a 1 k
Ω or lower value resistor from CLKSYN to GND may be needed to
increase fall time on CLKSYN pin.
CSO: The output of the current sense amplifier which is internally clamped to 4 V.
ENBL: The active low input with a 2.5-V threshold enables the output to switch. SEQ and RUN are driven low
when ENBL is above its 2.5-V threshold.
GND: The signal ground used for the voltage sense amplifier, current sense amplifier, current error amplifier,
voltage reference, 2X amplifier, and share amplifier. The output sink transistor is wired directly to this pin.
KILL: The active low input with a 3.0-V threshold stops the output from switching. Once this function is activated
RUN must be cycled low by driving KILL above 3.0 V and either resetting the power to the chip (VCC) or
resetting the ENBL signal.
ILIM: A voltage on this pin programs the voltage error amplifier’s Voh clamp. The voltage error amplifier output
represents the average output current. The Voh clamp consequently limits the output current. If ILIM is tied to
VREF, it defaults to 3.0 V. A voltage less than 3.0 V connected to ILIM clamps the voltage error amplifier at this
voltage and consequently limits the maximum output current.
OSC: The oscillator ramp pin which has a capacitor (CT) to ground and a resistor (RDEAD) to the RDEAD pin
programs its maximum duty cycle by programming a minimum dead time. The ramp oscillates between 1.2 V to
3.4 V when an RDEAD resistor is used. The maximum duty cycle can be increased by connecting RDEAD to
OSC which changes the oscillator ramp to vary between 0.2 V and 3.5 V. In order to ensure zero duty cycle in
this configuration VEE should not be connected to GND.
The charge time is approximately TCHARGE = RT • CT when the RDEAD resistor is used.
The dead time is approximately TDISCHARGE = 2 • RDEAD • CT.
The CT capacitance should be increased by approximately 40 pF to account for parasitic capacitance.
OUT: The output of the PWM driver. It has an upper clamp of 8.5 V. The peak current sink and source are 250
mA. All UVLO, SEQ, ENBL, and KILL logic either enable or disable the output driver.
6
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