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SI3216MPPQX-EVB Fiches technique(PDF) 2 Page - Silicon Laboratories |
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SI3216MPPQX-EVB Fiches technique(HTML) 2 Page - Silicon Laboratories |
2 / 41 page Si321xPPQx-EVB 2 Rev. 1.2 1. Introduction The ProSLIC Si321x evaluation platform is a modular system consisting of a generic motherboard and one or more Si321x device-specific daughter cards. Using the EVB hardware and ProSLIC LINC™ software, one can easily configure, control, and monitor Si321x operation. Up to eight Si321x daughter cards may be stacked vertically and accessed using uniquely-assigned timeslots on the common PCM interface and the SPI in daisy-chain mode. 1.1. ProSLIC LINC evaluation software The ProSLIC LINC software is an executable program that allows control and monitoring of the ProSLIC. It utilizes the primary LPT port of a standard PC to communicate to the ProSLIC’s SPI port. To install the software, insert the Silicon Laboratories ProSLIC CD into the computer. The setup routine can be invoked by running the setup.exe program in the root directory of the CD. Invoking the ProSLIC LINC is achieved by double clicking the ProSLIC LINC icon. Refer to the ProSLIC LINC User Guide for software operation. 1.2. Si321xPPT-EVB ProSLIC Evaluation Board Description Si321x EVB daughter cards currently supported by this hardware solution are listed in Table 1 along with supporting hardware schematics and layout references included in this data sheet. Motherboard hardware schematics are found in Figures 25, 26, and 27. All power and signal connections are made to the motherboard as described in Table 2. Signal requirements for ProSLIC operation are PCLK, FS, and Serial IO. The ProSLIC motherboard has a local oscillator with a programmable logic device to provide the ProSLIC PCLK FS signals. The DIP switch (S2) sets the PCLK frequency and controls the FS enable. See Table 3 for S2 settings. Factory default setting is for a 2.048 MHz PCLK with F5 enabled. JP3 and JP4 select this internal clock source or an external PCM clock source. The ProSLIC motherboard has been designed to directly connect to an Audio Precision SIA- 2322 Serial Interface Adapter through the 15 pin d- connectors, P2 and P3 (not installed). See Table 5 for the Audio Precision settings. The ProSLIC evaluation board has also been designed to interface with a Wandel and Goltermann PCM-4 through J8, J9, J10, and J11 (not installed). See Table 6 for PCM-4 settings. A header, J5 (not installed), allows access to the ProSLIC’s PCM signals for connection to other PCM testing devices or an actual telephone system PCM bus. TIP and RING of the two wire analog interface is present at the RJ-11 connector, J1. The ProSLIC evaluation board is voltage-programmable with specific jumper settings. JP1 selects 3 or 5 V ProSLIC operation. JP2 selects 3 or 5 V PCM source level compatibility. These should be placed on the expected setting. Table 4 shows a summary of JP1–4 settings. Power is connected to the ProSLIC at J3 and J4, and supply connections are summarized in Table 1. The 5 V is always required for the buffers, U2 and U3, to interface to the parallel port. The ProSLIC can be powered from 5 V or 3 V with the placement of a jumper on JP1. The Protection Return connections on J6 are to be connected to an appropriate ground for TIP/RING fault testing. This return is tied to signal ground on board, although it has a dedicated trace for high-current conditions. Serial control of the ProSLIC is achieved by toggling select bits of a standard parallel port. The parallel port connection is available at P1 and J1. The ProSLIC card can be daisy-chained by simply stacking the cards. Stack up to eight cards by aligning JS1–JS6 and pressing together. The ProSLIC LINC Software allows channel-specific commands by clicking the Daisy Chain button. Table 1. Supported Si321x EVB Daughter Cards EVB Daughter Card Board Description Schematic Figures Layout Figures Si3210/5/6 QFN with Si3201 integrated line interface 1, , 3 4, 5, 6 Si3210/5/6 QFN with discrete line interface 7, , 9 10, 11, 12 Si3210/5/6M QFN with Si3201 integrated line interface 13, 14, 15 16, 17, 18 Si3210/5/6M QFN with discrete line interface 19, 20, 21 22, 23, 24 |
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