M-88L70

www.clare.com

Rev. 1

3

ered a valid pause. This capability, together with the

ability to select the steering time constants externally,

allows the designer to tailor performance to meet a wide

variety of system requirements.

Guard Time Adjustment

Where independent selection of receive and pause are

not required, the simple steering circuit of Figure 3 is

applicable. Component values are chosen according to

the formula:

t

t

The value of t

the minimum signal duration to be recognized by the

receiver. A value for C of 0.1

µF is recommended for

most applications, leaving R to be selected by the

designer. For example, a suitable value of R for a t

40 ms would be 300 K ohm. A typical circuit using this

steering configuration is shown in Figure 4. The timing

requirements for most telecommunication applications

are satisfied with this circuit. Different steering arrange-

ments may be used to select independently the guard

times for tone-present (t

may be necessary to meet system specifications that

place both accept and reject limits on both tone duration

and interdigit pause.

Guard time adjustment also allows the designer to tailor

system parameters such as talkoff and noise immunity.

Increasing t

reduces the probability that tones simulated by speech

will maintain signal condition long enough to be regis-

tered. On the other hand, a relatively short t

long t

ronments where fast acquisition time and immunity to

dropouts would be required. Design information for

guard time adjustment is shown in Figure 5.

Input Configuration

The input arrangement of the M-88L70 provides a dif-

ferential input operational amplifier as well as a bias

source (V

made for connection of a feedback resistor to the op-

amp output (GS) for gain adjustment.

In a single-ended configuration, the input pins are con-

nected as shown in Figure 4 with the op-amp connect-

ed for unity gain and V

Figure 7 shows the differential configuration, which per-

mits gain adjustment with the feedback resistor R5.

Figure 3 Basic Steering Circuit

F

LOW

F

HIGH

Key

OE

INH

ESt

Q4

Q3

Q2

Q1

(ref.)

ANY

ANY

ANY

L

X

H

Z

Z

Z

Z

697

1209

1

H

X

H

0

0

0

1

697

1336

2

H

X

H

0

0

1

0

697

1477

3

H

X

H

0

0

1

1

770

1209

4

H

X

H

0

1

0

0

770

1336

5

H

X

H

0

1

0

1

770

1477

6

H

X

H

0

1

1

0

852

1209

7

H

X

H

0

1

1

1

852

1336

8

H

X

H

1

0

0

0

852

1477

9

H

X

H

1

0

0

1

941

1336

0

H

X

H

1

0

1

0

941

1209

*

H

X

H

1

0

1

1

941

1477

#

H

X

H

1

1

0

0

697

1633

A

H

L

H

1

1

0

1

770

1633

B

H

L

H

1

1

1

0

852

1633

C

H

L

H

1

1

1

1

941

1633

D

H

L

H

0

0

0

0

697

1633

A

H

H

L

Undetected, the output

770

1633

B

H

H

L

code will remain the

852

1633

C

H

H

L

same as the previous

941

1633

D

D

H

L

detected code.

L = logic low, H = logic high, Z = high impedance, X = don’t care

Table 2 Tone Decoding