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CDB4360 Fiches technique(PDF) 3 Page - Cirrus Logic

No de pièce CDB4360
Description  24-Bit, 192 kHz 6 Channel D/A Converter?
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Fabricant  CIRRUS [Cirrus Logic]
Site Internet  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB4360 Fiches technique(HTML) 3 Page - Cirrus Logic

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CS4360
DS517PP1
3
4.6.1 Revision Indicator (REV) [Read Only] ........................................................................... 19
5. PIN DESCRIPTION.................................................................................................................. 20
6. APPLICATIONS ...................................................................................................................... 23
6.1 Grounding and Power Supply Decoupling........................................................................ 23
6.2 Oversampling Modes........................................................................................................ 23
6.3 Recommended Power-up Sequence................................................................................ 23
6.4 Popguard® Transient Control........................................................................................... 23
7. CONTROL PORT INTERFACE............................................................................................... 24
7.1 Enabling the Control Port ................................................................................................. 24
7.2 Format Selection .............................................................................................................. 24
7.3 Two-Wire Format .............................................................................................................. 24
7.3.1 Writing in Two-Wire Format ................................................................................. 24
7.3.2 Reading in Two-Wire Format ............................................................................... 25
7.4 SPI Format ....................................................................................................................... 25
7.4.1 Writing in SPI ....................................................................................................... 25
7.5 Memory Address Pointer (MAP) ...................................................................................... 26
7.5.1 INCR (Auto Map Increment Enable) .............................................................................. 26
7.5.2 MAP (Memory Address Pointer) .................................................................................... 26
8. PARAMETER DEFINITIONS................................................................................................... 32
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 32
Dynamic Range ...................................................................................................................... 32
Interchannel Isolation ............................................................................................................. 32
Interchannel Gain Mismatch ................................................................................................... 32
Gain Error ............................................................................................................................... 32
Gain Drift ................................................................................................................................ 32
9. REFERENCES......................................................................................................................... 32
10. PACKAGE DIMENSIONS ..................................................................................................... 33
LIST OF FIGURES
Figure 1.
Serial Mode Input Timing ............................................................................................... 9
Figure 2.
Control Port Timing - Two-Wire Format ....................................................................... 10
Figure 3.
Control Port Timing - SPI Format ................................................................................. 11
Figure 4.
Typical Connection Diagram ........................................................................................ 12
Figure 5.
Control Port Timing, Two-Wire Format ........................................................................ 25
Figure 6.
Control Port Timing, SPI Format .................................................................................. 25
Figure 7.
Base-Rate Stopband Rejection .................................................................................... 27
Figure 8.
Base-Rate Transition Band .......................................................................................... 27
Figure 9.
Base-Rate Transition Band (Detail) ............................................................................. 27
Figure 10. Base-Rate Passband Ripple ........................................................................................ 27
Figure 11. High-Rate Stopband Rejection .................................................................................... 27
Figure 12. High-Rate Transition Band ........................................................................................... 27
Figure 13. High-Rate Transition Band (Detail) .............................................................................. 28
Figure 14. High-Rate Passband Ripple ......................................................................................... 28
Figure 15. Output Test Load ......................................................................................................... 28
Figure 16. Maximum Loading ........................................................................................................ 28
Figure 17. CS4360 Format 0 - Left Justified upto 24-bit Data ....................................................... 29
Figure 18. CS4360 Format 1 - I2S upto 24-bit Data ...................................................................... 29
Figure 19. CS4360 Format 2 - Right Justified 16-bit Data ............................................................ 29
Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ............................................................ 29
Figure 21. CS4360 Format 4 - Right Justified 20-bit Data ............................................................ 30


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