 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
CS4202 Fiches technique(PDF) 19 Page - Cirrus Logic |
|
||||||||||||||||||||||||||||||
CS4202 Fiches technique(HTML) 19 Page - Cirrus Logic |
|
|
19 / 68 page  CS4202 DS549PP1 19 3.2.3 Status Data Port (Slot 2) RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following serial data frame. 3.2.4 PCM Capture Data (Slot 3-4,6-8,11) CD[17:0] Capture Data. The CD [17:0] bits contain 18-bit PCM (2’s complement) capture data. The data will only be valid when the respective slot valid bit is ‘set’ in input Slot 0. The mapping of a given slot to an ADC is determined by the state of the ASA[1:0] bits in the AC Mode Control Register (index 5Eh). The definition of each slot can be found in Table 8 on page 30. 3.2.5 GPIO Pin Status (Slot 12) GPIO[4:0] GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4202 GPIO pins configured as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[4:0] pin control bits in output Slot 12. BDI BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the BDI Config Register (Index 70h). GPIO_INT GPIO Interrupt. The GPIO_INT bit indicates that a GPIO or BDI interrupt event has occurred. The occurrence of a GPIO interrupt is determined by the GPIO interrupt requirements as out- lined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the GPIO Pin Status Register (Index 54h) corresponding to the GPIO pin which generated the interrupt. The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined in the BDI Control Registers (Index 70h - 72h). In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the BDI Status Register (Index 7Ah) that generated the interrupt. Bit 19 18 17 16 15 14 13 12 11 10 9876 54 3210 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reserved Bit 19 18 17 16 15 14 13 12 11 10 98765 4321 0 CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 0 0 Bit 19 18 17 16 15 14 13 12 11 10 9 87654 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Res BDI Res GPIO _INT |
Numéro de pièce similaire - CS4202 |
|
Description similaire - CS4202 |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
