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CS5157HGD16 Fiches technique(PDF) 10 Page - Cherry Semiconductor Corporation |
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CS5157HGD16 Fiches technique(HTML) 10 Page - Cherry Semiconductor Corporation |
10 / 14 page Applications Information: continued 10 Figure 13: OVP response to an input-to-output short circuit by pulling the input voltage to ground. External Output Enable Circuit On/off control of the regulator can be implemented through the addition of two additional discrete compo- nents (see Figure 14). This circuit operates by pulling the soft start pin high, and the VFFB pin low, emulating a short circuit condition. Figure 14: Implementing shutdown with the CS5157H. External Power Good Circuit An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation: VPower Good = This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good. Figure 15: Implementing Power Good with the CS5157H. Figure 16: CS5157H demonstration board during power up. Power Good signal is activated when output voltage reaches 1.70V. Selecting External Components The CS5157H can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12V supply which is generally available in most computer systems and utilize logic level MOSFETs. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and ther- mal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5V of ground when in the low state and to within 2V of their respective bias supplies when in the high state. In practice, the MOS- FET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12V and 5V is Trace 3 = 12V Input (VCC1) and VCC2) (10V/div.) Trace 4 = 5V Input (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.) Trace 2 = Power Good Signal (2V/div.) Ch 1 High 2.80V VOUT CS5157H R1 10k R2 6.2k R3 10k Power Good 5V PN3904 PN3904 (R1 + R2) × 0.65V R2 Shutdown Input 5V VFFB CS5157H SS 5 8 IN4148 MMUN2111T1 (SOT-23) Trace 4 = 5V from PC Power Supply (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.) |
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Description similaire - CS5157HGD16 |
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