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ML9059E Fiches technique(PDF) 16 Page - List of Unclassifed Manufacturers

No de pièce ML9059E
Description  132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
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ML9059E Fiches technique(HTML) 16 Page - List of Unclassifed Manufacturers

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FEDL9059E-01
LAPIS Semiconductor
ML9059E
16/72
Function
Pin name
Number
of pins
I/O
Description
This is the pin for selecting parallel data input or serial data input.
P/S = “H”: Parallel data input.
P/S = “L”: Serial data input.
The pins of the LSI have the following functions depending on the
state of P/S input.
P/S
Data/command
Data
Read/Write
Serial clock
“H”
A0
DB0 to DB7
RD, WR
“L”
A0
SI (D7)
SCL(DB6)
MPU
Interface
P/S
1
I
During serial data input, it is not possible to read the display data in
the RAM
Oscillator
circuit
CLS
1
I
This is the pin for selecting whether to enable or disable the
internal oscillator circuit for the display clock.
CLS = “H”: The internal oscillator circuit is enabled.
CLS = “L”: The internal oscillator circuit is disabled (External input).
When CLS = “L”, the display clock is input at the pin CL.
This is the pin for selecting whether master operation or slave
operation is made towards the ML9059E. During slave operation,
the synchronization with the LCD display system is achieved by
inputting the timing signals necessary for LCD display.
M/S = “H”: Master operation
M/S = “L”: Slave operation
The functions of the different circuits and pins will be as follows
depending on the states of M/S and CLS signals.
M/S
CLS
Oscillator
circuit
Power
supply circuit
CL
FR
FRS
DOF
“H”
Enabled
Enabled
Output
Output
Output
Output
“H”
“L”
Disabled
Enabled
Input
Output
Output
Output
“H”
Disabled
Disabled
Input
Input
Output
Input
“L”
“L”
Disabled
Disabled
Input
Input
Output
Input
Display
timing
generator
circuit
M/S
1
I


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