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CAT24C162JA-28TE13 Fiches technique(PDF) 5 Page - Catalyst Semiconductor |
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CAT24C162JA-28TE13 Fiches technique(HTML) 5 Page - Catalyst Semiconductor |
5 / 12 page CAT24CXX1/XX2 5 Advanced Doc. No. 25079-00 1/98 M-1 PIN DESCRIPTIONS WP: WRITE PROTECT If the pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the pin is tied to VSS or left floating normal read/write operations are allowed to the device. SCL: SERIAL CLOCK The serial clock input clocks all data transferred into or out of the device. RESET/ RESET RESET RESET RESET RESET: RESET I/O These are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition for approximately 200ms. RESET pin must be connected through a pull-down and RESET pin must be connected through a pull-up device. SDA: SERIAL DATA/ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. In the 24CXX1, the SDA line is also used as the Watchdog Timer Monitor. Reset Controller Description The CAT24CXXX provides a precision RESET control- ler that ensures correct system operation during brown- out and power-up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID). The RESET pins are I/Os; therefore, the CAT24CXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 24CXXX will initiate a reset timeout after detecting a high and the RESET input in the 24CXXX will initiate a reset timeout after detecting a low. Watchdog Timer The Watchdog Timer provides an independent protec- tion for microcontrollers. During a system failure, the CAT24CXX1 will respond with a reset signal after a time- out interval of 1.6 seconds for lack of activity. 24CXX1 is designed with the Watchdog Timer feature on the SDA input. For the 24CXX1, if the microcontroller does not toggle the SDA input pin within 1.6 seconds the Watch- dog Timer times out. This will generate a reset condition on reset outputs. The Watchdog Timer is cleared by any transition on SDA. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. 24CXX2 does not feature the Watchdog Timer function. Figure 1. RESET Output Timing DEVICE OPERATION GLITCH t VCC PURST t PURST t RPD t RVALID V V TH RESET RESET RPD t |
Numéro de pièce similaire - CAT24C162JA-28TE13 |
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Description similaire - CAT24C162JA-28TE13 |
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