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CAT28F001TI-15BT Fiches technique(PDF) 5 Page - Catalyst Semiconductor

No de pièce CAT28F001TI-15BT
Description  1 Megabit CMOS Boot Block Flash Memory
Download  18 Pages
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Fabricant  CATALYST [Catalyst Semiconductor]
Site Internet  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT28F001TI-15BT Fiches technique(HTML) 5 Page - Catalyst Semiconductor

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CAT28F001
5
Doc. No. 25071-00 2/98 F-1
SUPPLY CHARACTERISTICS
Limits
Symbol
Parameter
Min
Max.
Unit
VLKO
VCC Erase/Write Lock Voltage
2.5
V
VCC
VCC Supply Voltage
4.5
5.5
V
VPPL
VPP During Read Operations
0
6.5
V
VPPH
VPP During Erase/Program
11.4
12.6
V
VHH
RP, OE Unlock Voltage
11.4
12.6
V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
JEDEC
Standard
28F001-90(7)
28F001-12(7)
28F001-15(7)
Symbol
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tAVAV
tRC
Read Cycle Time
90
120
150
ns
tELQV
tCE
CE Access Time
90
120
150
ns
tAVQV
tACC
Address Access Time
90
120
150
ns
tGLQV
tOE
OE Access Time
35
50
55
ns
-tOH
Output Hold from Address OE/CE Change
0
0
0
ns
tGLQX
tOLZ(1)(6)
OE to Output in Low-Z
0
0
0
ns
tELQX
tLZ(1)(6)
CE to Output in Low-Z
0
0
0
ns
tGHQZ
tDF(1)(2)
OE High to Output High-Z
30
30
30
ns
tEHQZ
tHZ(1)(2)
CE High to Output High-Z
35
55
55
ns
tPHQV
tPWH
RP High to Output Delay
600
600
600
ns
28F001-70(8)
Min.
Max.
0
0
0
70
70
70
27
30
55
600
5108 FHD F05
Note:
(1)
This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3)
Input Rise and Fall Times (10% to 90%) < 10 ns.
(4)
Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5)
Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6)
Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7)
For load and reference points, see Fig. 1
(8)
For load and reference points, see Fig. 2
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS
REFERENCE POINTS
2.0 V
0.8 V
2.4 V
0.45 V
5108 FHD F03A
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
Testing Load Circuit (example)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
INPUT PULSE LEVELS
REFERENCE POINTS
3.0 V
0.0 V
1.5 V
5108 FHD F03
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
Testing Load Circuit (example)


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