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CAT28C65BK-12T Fiches technique(PDF) 7 Page - Catalyst Semiconductor |
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CAT28C65BK-12T Fiches technique(HTML) 7 Page - Catalyst Semiconductor |
7 / 11 page CAT28C65B 7 Doc. No. 25036-00 2/98 ADDRESS CE OE WE tRC DATA OUT DATA VALID DATA VALID tCE tOE tOH tAA tOHZ tHZ VIH HIGH-Z tLZ tOLZ DEVICE OPERATION Read Data stored in the CAT28C65B is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WEare low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the Figure 3. Read Cycle 28C65B F06 Figure 4. Byte Write Cycle [ WE WE WE WE WE Controlled] 5099 FHD F06 ADDRESS CE OE WE DATA OUT tAS DATA IN DATA VALID HIGH-Z tCS tAH tCH tWC tOEH tBLC tDH tDS tWP RDY/BUSY tOES tRB HIGH-Z HIGH-Z |
Numéro de pièce similaire - CAT28C65BK-12T |
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Description similaire - CAT28C65BK-12T |
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