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CAT25C17UI-1.8TE13 Fiches technique(PDF) 5 Page - Catalyst Semiconductor |
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CAT25C17UI-1.8TE13 Fiches technique(HTML) 5 Page - Catalyst Semiconductor |
5 / 10 page 5 CAT25C03/05/09/17/33 Doc. No. 25068-00 2/98 Advanced 76543210 00000 IDL2 IDL1 IDL0 STATUS REGISTER brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. ( HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence. IDL2 IDL1 IDL0 0 0 0 Non-Protection 0 0 1 Q1 Protected 0 1 0 Q2 Protected 0 1 1 Q3 Protected 1 0 0 Q4 Protected 1 0 1 H1 Protected 1 1 0 P0 Protected 1 1 1 Pn Protected 25C03 25C05 25C09 25C17 25C33 Q1 00-3F 000-07F 000-0FF 000-1FF 000-3FF Q2 40-7F 080-0FF 100-1FF 200-3FF 400-7FF Q3 80-BF 100-17F 200-2FF 400-5FF 800-BFF Q4 C0-FF 180-1FF 300-3FF 600-7FF C00-FFF H1 00-7F 000-0FF 000-1FF 000-3FF 000-7FF P0 00-0F 000-00F 000-01F 000-01F 000-01F Pn F0-FF 1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF STATUS REGISTER The status register defines the protection status of the device. The register features three protection bits which allow the user to protect the desirable part of the memory array. There are seven different variations for the protec- tion mechanism. The protection can vary from one page to as much as half of the entire array. These areas and associated address ranges are protected by configuring the protection bits of the status register through WRSR instruction. Once the three protection bits are set, the associated memory can be read but not written until the protection bits are reset. MEMORY PROTECTION |
Numéro de pièce similaire - CAT25C17UI-1.8TE13 |
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Description similaire - CAT25C17UI-1.8TE13 |
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