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J108 Fiches technique(PDF) 1 Page - Calogic, LLC

No de pièce J108
Description  N-Channel JFET Switch
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Fabricant  CALOGIC [Calogic, LLC]
Site Internet  http://www.calogic.net
Logo CALOGIC - Calogic, LLC

J108 Fiches technique(HTML) 1 Page - Calogic, LLC

  J108 Datasheet HTML 1Page - Calogic, LLC  
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N-Channel JFET Switch
J108 – J110 / SST108 – SST110
FEATURES
•• Low Cost
•• Automated Insertion Package
•• Low Insertion Loss
•• No OffsetorErrorVoltagesGeneratedby Closed Switch
Purely Resistive
High Isolation Resistance from Driver
•• Fast Switching
•• Low Noise
APPLICATIONS
•• Analog Switches
•• Choppers
•• Commutators
•• Low-Noise Audio Amplifiers
ABSOLUTE MAXIMUM RATINGS
(TA = 25
oC unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55
oC to +150oC
Operating Temperature Range . . . . . . . . . . . -55
oC to +135oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300
oC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25
oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part
Package
Temperature Range
J108-110
Plastic TO-92
-55
oC to +135oC
XJ108-110
Sorted Chips in Carriers
-55
oC to +135oC
SST109-110 Plastic SOT-23
-55
oC to +135oC
CORPORATION
PIN CONFIGURATION
TO-92
S G
D
5018
ELECTRICAL CHARACTERISTICS (TA = 25
oC unless otherwise specified)
SYMBOL
PARAMETER
108
109
110
UNITS
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
IGSS
Gate Reverse Current (Note 1)
-3
-3
-3
nA
VDS = 0V, VGS = -15V
VGS(off)
Gate-Source Cutoff Voltage
-3
-10
-2
-6
-0.5
-4
V
VDS = 5V, ID = 1
µA
BVGSS
Gate-Source Breakdown Voltage
-25
-25
-25
VDS = 0V, IG = -1
µA
IDSS
Drain Saturation Current (Note 2)
80
40
10
mA
VDS = 15V, VGS = 0V
ID(off)
Drain Cutoff Current (Note 1)
3
3
3
nA
VDS = 5V, VGS = -10V
rDS(on)
Drain-Source ON Resistance
8
12
18
VDS
≤0.1V, VGS = 0V
Cdg(off)
Drain-Gate OFF Capacitance
15
15
15
pF
VDS = 0,
VGS = -10V
(Note 3)
f = 1MHz
Csg(off)
Source-Gate OFF Capacitance
15
15
15
Cdg(on)
+ Csg(on)
Drain-Gate Plus Source-Gate
ON Capacitance
85
85
85
VDS = VGS = 0
(Note 3)
td(on)
Turn On Delay Time
4
4
4
ns
Switching Time Test
Conditions (Note 3)
J107
J109
J110
VDD
1.5V1.5V1.5V
VGS(off) -12V
-7V
-5V
RL
150
150
150
tr
Rise Time
1
1
1
td(off)
Turn OFF Delay Time
6
6
6
tf
Fall Time
30
30
30
NOTES: 1. Approximately doubles for every 10
oC increase in TA.
2. Pulse test duration = 300
µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
PRODUCT MARKING (SOT-23)
SST108
I 08
SST109
I 09
SST110
I 10
SOT-23
G
S
D


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