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AFE1104

1

AFE1104E

HDSL/MDSL ANALOG FRONT END

FEATURES

q COMPLETE ANALOG INTERFACE

q T1, E1, AND MDSL OPERATION

q CLOCK SCALEABLE SPEED

q SINGLE CHIP SOLUTION

q +5V ONLY (5V OR 3.3V DIGITAL)

q 250mW POWER DISSIPATION

q 48-PIN SSOP

q –40

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the

size and cost of an HDSL or MDSL system by provid-

ing all of the active analog circuitry needed to connect

PairGain Technologies SPAROW HDSL digital sig-

nal processor to an external compromise hybrid and a

1:2 HDSL line transformer. All internal filter re-

sponses as well as the pulse former output scale with

clock frequency—allowing the AFE1104 to operate

over a range of bit rates from 196kbps to 1.168Mbps.

Functionally, this unit is separated into a transmit and

a receive section. The transmit section generates, fil-

ters, and buffers outgoing 2B1Q data. The receive

section filters and digitizes the symbol data received

on the telephone line and passes it to the SPAROW.

The HDSL Analog Interface is a monolithic device

fabricated on 0.6

µCMOS. It operates on a single +5V

supply. It is housed in a 48-pin SSOP package.

PDS-1331A

Printed in U.S.A. August, 1996

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

AFE1104

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Pulse

Former

txDAT

txCLK

rxGAIN

rxD13 - rxD0

Line

Driver

Voltage

Reference

Delta-Sigma

Modulator

Transmit

Control

rxSYNC

rxCLK

rxLOOP

Receive

Control

Decimation

Filter

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Patents Pending