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ATMEGA603 Fiches technique(PDF) 5 Page - ATMEL Corporation |
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ATMEGA603 Fiches technique(HTML) 5 Page - ATMEL Corporation |
5 / 10 page ATmega603(L) and ATmega103(L) 5 Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture The AVR uses a Harvard architecture concept - with sepa- rate memories and buses for program and data. The pro- gram memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and conse- quently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initial- ize the SP in the reset routine (before subroutines or inter- rupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space. The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector posi- tion. The lower the interrupt vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps. The General Purpose Register File Figure 5 shows the structure of the 32 general purpose working registers in the CPU. 32K/64K x 16 Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registers ALU Status and Test 2K/4K x 8 EEPROM Peripherals Data Bus 8-bit AVR ATmega603/103 Architecture 4K x 8 Data SRAM |
Numéro de pièce similaire - ATMEGA603 |
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Description similaire - ATMEGA603 |
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