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74LVT125D-T Fiches technique(PDF) 1 Page - NXP Semiconductors |
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74LVT125D-T Fiches technique(HTML) 1 Page - NXP Semiconductors |
1 / 16 page 1. General description The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one of the 3-state outputs. 2. Features I Quad bus interface I 3-state buffers I Output capability: +64 mA and −32 mA I TTL input and output switching levels I Input and output interface capability to systems at 5 V supply I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs I Live insertion and extraction permitted I No bus current loading when output is tied to 5 V bus I Power-up 3-state I Latch-up protection: N JESD78: exceeds 500 mA I ESD protection: N MIL STD 883 method 3015: exceeds 2000 V N Machine model: exceeds 200 V 3. Quick reference data 74LVT125; 74LVTH125 3.3 V quad buffer; 3-state Rev. 06 — 6 March 2006 Product data sheet Table 1. Quick reference data GND = 0 V; Tamb =25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH LOW-to-HIGH propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.7 - ns tPHL HIGH-to-LOW propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.9 - ns |
Numéro de pièce similaire - 74LVT125D-T |
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